SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
2.4
Electrical Characteristics
(3.15 V < V
CC
< 3.45 V, -40 °C < T
A
< 85 °C. Typical values at V
CC
= 3.3 V, T
A
= 25 °C, at the Recommended Operating
Conditions and are
not
assured.)
Symbol
I
CC_PD
I
CC_CLKS
Parameter
Power Down Supply Current
Supply Current
(1)
Conditions
Current Consumption
Min
Typ
1
Max
3
665
Units
mA
mA
14 HSDS 8 mA clocks enabled
PLL1 and PLL2 locked.
0.001
20% to 80%
AC coupled
AC coupled to CLKinX;
CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 0 (Bipolar)
AC coupled to CLKinX;
CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
Each pin AC coupled, CLKin0/1/2
CLKin0_BUF_TYPE = 0 (Bipolar)
Each pin AC coupled, CLKin0/1
CLKinX_BUF_TYPE = 1 (MOS)
Each pin AC coupled
CLKin2_BUF_TYPE = 1 (MOS)
DC coupled to CLKinX;
CLKinX* AC coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
AC coupled
CLKin1_BUF_TYPE = 0 (Bipolar)
AC coupled
(4)
CLKin1_BUF_TYPE = 0 (Bipolar)
AC coupled
CLKin1_BUF_TYPE = 0 (Bipolar)
AC coupled; 20% to 80%;
(CLKinX_BUF_TYPE = 0)
2.0
0.0
0.15
0.125
0.25
0.25
565
CLKin0/0*, CLKin1/1*, and CLKin2/2* Input Clock Specifications
f
CLKin
SLEW
CLKin
V
ID
CLKin
V
SS
CLKin
Clock Input Frequency
Clock Input Slew Rate
(2)
750
0.5
1.55
3.1
2.4
MHz
V/ns
|V|
Vpp
Vpp
Clock Input
Differential Input Voltage
(3)
V
CLKin
Clock Input
Single-ended Input Voltage
0.35
0
55
20
2.4
Vpp
|mV|
|mV|
|mV|
|V
CLKinX-offset
|
DC offset voltage between
CLKinX/CLKinX* (CLKinX* - CLKinX)
DC offset voltage between
CLKin2/CLKin2* (CLKin2* - CLKin2)
V
CLKin-
V
IH
V
CLKin-
V
IL
High input voltage
Low input voltage
V
CC
0.4
V
V
FBCLKin/FBCLKin* and Fin/Fin* Input Specifications
f
FBCLKin
f
Fin
V
FBCLKin/Fin
SLEW
FBCLKin/Fin
(1)
(2)
Clock Input Frequency for
0-delay with external feedback.
Clock Input Frequency for
external VCO or distribution mode.
Single Ended
Clock Input Voltage
Slew Rate on CLKin
(2)
0.001
0.001
0.25
0.15
0.5
750
3100
2.0
MHz
MHz
Vpp
V/ns
(3)
(4)
See applications section
for Icc for specific part configuration and how to calculate Icc for a specific design.
In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended
clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to
their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to
achieve optimal phase noise performance at the device outputs.
See
for definition of V
ID
and V
OD
voltages.
Assured by characterization. ATE tested at 2949.12 MHz.
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
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