SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
1
2
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1.1
Features
.............................................
1.2
Applications
..........................................
1.3
Description
...........................................
1.4
Device Configuration Information
....................
1.5
Functional Block Diagrams and Operating Modes
..
1.6
Connection Diagram
.................................
7
ELECTRICAL SPECIFICATIONS
....................
2.1
Absolute Maximum Ratings
........................
2.2
Package Thermal Resistance
......................
2.3
Recommended Operating Conditions
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2.4
Electrical Characteristics
...........................
2.5
SPI Timing Diagram
................................
2.6
Differential Voltage Measurement Terminology
....
INTRODUCTION
TYPICAL PERFORMANCE CHARACTERISTICS
5
3
4
6
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FEATURES
..............................................
4.1
Jitter Cleaning
......................................
4.2
JEDEC JESD204B Support
........................
3.1
Clock Output AC Characteristics
4.3
7
Three PLL1 Redundant Reference Inputs
(CLKin0/CLKin0*, CLKin1/CLKin1*, and
CLKin2/CLKin2*)
...................................
4.4
4.5
4.6
.....................
Frequency Holdover
................................
PLL2 Integrated Loop Filter Poles
..................
VCXO/Crystal Buffered Output
......................................
4.8
External VCO Mode
................................
4.9
Clock Distribution
...................................
4.10 0-Delay
.............................................
4.11 Status Pins
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FUNCTIONAL DESCRIPTIONS
......................
5.1
Modes Of Operation
................................
5.2
SYNC/SYSREF
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5.3
JEDEC JESD204B
.................................
5.4
Digital Delay
........................................
5.5
SYSREF to Device Clock Alignment
...............
5.6
Input Clock Switching
...............................
5.7
Digital Lock Detect
..................................
5.8
Holdover
............................................
GENERAL PROGRAMMING INFORMATION
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6.1
Recommended Programming Sequence
...........
6.2
Register Map
.......................................
6.3
Device Register Descriptions
.......................
APPLICATION INFORMATION
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7.1
Digital Lock Detect Frequency Accuracy
...........
7.2
Pin Connection Recommendations
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7.3
Driving CLKin AND OSCin Inputs
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7.4
Power Supply
.......................................
7.5
Thermal Management
..............................
4.7
Internal VCOs
Copyright © 2013, Texas Instruments Incorporated
Contents
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