MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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Functional Block Diagram, MSP430F673xIPZ, MSP430F672xIPZ
PB
PA
P3.x
PC
PD
PE
P9.x
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P4.x
P5.x P6.x
P7.x P8.x
P1.x P2.x
(32kHz)
ACLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
I/O Ports
P7/P8
2×8 I/Os
I/O Ports
P9
1×4 I/O
SYS
Unified
Clock
System
8kB
4KB
2KB
1KB
128kB
96KB
64KB
32KB
16KB
Watchdog
CRC16
MPY32
SMCLK
Port
Mapping
Controller
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
PD
1×16 I/Os
PE
1×4 I/O
RAM
Flash
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
TA1
TA2
TA3
LCD_C
ADC10_A
REF
SD24_B
eUSCI_B0
(SPI, I2C)
TA0
DMA
JTAG/
SBW
Interface/
RTC_C
8MUX
Up to 320
Segments
3 Channel
10 Bit
200 KSPS
Reference
1.5V, 2.0V,
2.5V
3 Channel
2 Channel
LDO
SVM/SVS
BOR
(UART,
IrDA,SPI)
Timer_A
2 CC
Registers
Timer_A
3 CC
Registers
Port PJ
Functional Block Diagram, MSP430F673xIPN, MSP430F672xIPN
PB
PC
PA
DVCC DVSS AVCC AVSS
AUX1 AUX2 AUX3
XIN
XOUT
RST/NMI
P3.x
P4.x
P5.x P6.x
P1.x P2.x
(32kHz)
ACLK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
2×8 I/Os
I/O Ports
P5/P6
2×8 I/Os
SYS
Watchdog
Unified
Clock
System
8KB
4KB
2KB
1KB
128KB
96KB
64KB
32KB
16KB
DMA
CRC16
MPY32
SMCLK
3 Channel
Port
Mapping
Controller
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×16 I/Os
MCLK
RAM
Flash
CPUXV2
and
Working
Registers
(25MHz)
EEM
(S: 3+1)
TA1
TA2
TA3
PMM
Auxiliary
Supplies
eUSCI_A0
eUSCI_A1
eUSCI_A2
LCD_C
ADC10_A
REF
SD24_B
TA0
eUSCI_B0
(SPI, I2C)
JTAG/
SBW
Interface/
RTC_C
8MUX
Up to 320
Segments
10 Bit
200 KSPS
Reference
1.5V, 2.0V,
2.5V
3 Channel
2 Channel
Timer_A
3 CC
Registers
Timer_A
2 CC
Registers
LDO
SVM/SVS
BOR
(UART,
IrDA,SPI)
Port PJ
4
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