MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Pin Designation, MSP430F673xIPZ
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
SD0P0
1
75 DVSS
SD0N0
2
74 DVSYS
SD1P0
3
73 P6.0/S19
SD1N0
4
72 P5.7/S20
SD2P0
5
71 P5.6/S21
SD2N0
6
70 P5.5/S22
VREF
7
69 P5.4/S23
AVSS
8
68 P5.3/S24
AVCC
9
67 P5.2/S25
VASYS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
66 P5.1/S26
P9.1/A5
65 P5.0/S27
P9.2/A4
64 P4.7/S28
P9.3/A3
PZ PACKAGE
63 P4.6/S29
P1.0/PM_TA0.0/VeREF-/A2
62 P4.5/S30
P1.1/PM_TA0.1/VeREF+/A1
61 P4.4/S31
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
60 P4.3/S32
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
59 P4.2/S33
AUXVCC2
AUXVCC1
VDSYS
DVCC
58 P4.1/S34
57 P4.0/S35
56 P3.7/PM_SD2DIO/S36
55 P3.6/PM_SD1DIO/S37
54 P3.5/PM_SD0DIO/S38
53 P3.4/PM_SDCLK/S39
52 P3.3/PM_TA0.2
51 P3.2/PM_TACLK/PM_RTCCLK
DVSS
VCORE
XIN
XOUT
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
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