MSP430F673x
MSP430F672x
www.ti.com
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Pin Designation, MSP430F673xIPN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SD0P0
1
2
60 DVSS
SD0N0
59 DVSYS
SD1P0
3
58 P5.1/S14
SD1N0
4
57 P5.0/S15
SD2P0
5
56 P4.7/S16
SD2N0
6
55 P4.6/S17
VREF
7
54 P4.5/S18
AVSS
8
53 P4.4/S19
AVCC
9
52 P4.3/S20
VASYS
10
11
12
13
14
15
16
17
18
19
20
51 P4.2/S21
PN PACKAGE
P1.0/PM_TA0.0/VeREF-/A2
50 P4.1/S22
P1.1/PM_TA0.1/VeREF+/A1
49 P4.0/S23
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
48 P3.7/PM_SD2DIO/S24
47 P3.6/PM_SD1DIO/S25
46 P3.5/PM_SD0DIO/S26
45 P3.4/PM_SDCLK/S27
44 P3.3/PM_TA0.2/S28
43 P3.2/PM_TACLK/PM_RTCCLK/S29
42 P3.1/PM_TA2.1/S30/BSL_RX
41 P3.0/PM_TA2.0/S31/BSL_TX
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
DVCC
DVSS
VCORE
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See Table 14 for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
TI [ TEXAS INSTRUMENTS ]
