MSP430G2x52
MSP430G2x12
SLAS722B
–
DECEMBER 2010
–
REVISED MARCH 2011
Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
00h
7
6
5
ACCVIE
rw-0
WDTIE
OFIE
NMIIE
ACCVIE
Address
01h
4
NMIIE
rw-0
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
Table 7. Interrupt Flag Register 1 and 2
Address
02h
7
6
5
4
NMIIFG
rw-0
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
03h
3
RSTIFG
rw-(0)
2
PORIFG
rw-(1)
1
OFIFG
rw-1
0
WDTIFG
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-On Reset interrupt flag. Set on V
CC
power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
CC
power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
10
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