MSP430G2x52
MSP430G2x12
SLAS722B
–
DECEMBER 2010
–
REVISED MARCH 2011
Table 2. Terminal Functions (continued)
TERMINAL
NO.
NAME
P1.7/
CAOUT/
SDI/
SDA/
A7/
CA7/
TDO/TDI
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
XIN/
P2.6/
TA0.1
XOUT/
P2.7
RST/
NMI/
SBWTDIO
TEST/
11
SBWTCK
DVCC
AVCC
DVSS
AVSS
NC
QFN Pad
(2)
(3)
1
-
14
-
-
-
16
15
14
13
-
Pad
1
-
20
-
-
-
NA
NA
NA
NA
NA
NA
10
17
I
10
9
16
I
12
11
18
I/O
13
12
19
I/O
(2)
I/O
20
N, PW
General-purpose digital I/O pin
Comparator_A+, output
USI: Data input in SPI mode
DESCRIPTION
14
PW
16
RSA
9
8
15
I/O
USI: I2C data in I2C mode
ADC10 analog input A7
(1)
Comparator_A+, CA7 input
JTAG test data output terminal or test data input during programming and test
-
-
-
-
-
-
-
-
-
-
-
-
8
9
10
11
12
13
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
General-purpose digital I/O pin
Input terminal of crystal oscillator
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator
(3)
General-purpose digital I/O pin
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
Supply voltage
Supply voltage
Ground reference
Ground reference
Not connected
QFN package pad connection to V
SS
recommended.
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
6
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