MSP430G2x52
MSP430G2x12
SLAS722B
–
DECEMBER 2010
–
REVISED MARCH 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range
(1)
NMI
Oscillator fault
Flash memory access violation
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(2)
NMIIFG
OFIFG
ACCVIFG
(2) (3)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
0FFFAh
0FFF8h
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15 to 0, lowest
Comparator_A+
Watchdog Timer+
Timer0_A3
Timer0_A3
CAIFG
(4)
WDTIFG
TACCR0 CCIFG
(4)
TACCR2 TACCR1 CCIFG. TAIFG
(2) (4)
maskable
maskable
maskable
maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
ADC10
USI
(5)
ADC10IFG
(4) (5)
maskable
maskable
maskable
maskable
(2) (4)
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
USIIFG, USISTTIFG
(2) (4)
P2IFG.0 to P2IFG.7
P1IFG.0 to P1IFG.7
(2) (4)
I/O Port P2 (up to eight flags)
I/O Port P1 (up to eight flags)
See
(1)
(2)
(3)
(4)
(5)
(6)
(6)
0FFDEh to
0FFC0h
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
MSP430G2x52 only
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright
©
2010–2011, Texas Instruments Incorporated
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