ELECTRICAL CHARACTERISTICS
All specifications at +25°C, +V
CA
= +V
DD
= +V
CP
= +5V, f
S
= 44.1kHz, and 16-bit input data, SYSCLK = 384f
S
, unless otherwise noted.
PCM1727
PARAMETER
RESOLUTION
DATA FORMAT
Audio Data Interface Format
Data Bit Length
Audio Data Format
Sampling Frequency (f
S
)
PLL PERFORMANCE
Master Clock Input Frequency
(4)
Generated System Clock
SCKO-1
SCKO-2
SCKO-3
Output Logic Level
V
OH
(MCKO, SCKO 1 ~ 3)
V
OL
Generated SYSCLK Jitter
Generated SYSCLK Transient
(1)
Power-Up Time
Generated SYSCLK Duty Cycle
DIGITAL INPUT LOGIC LEVEL
DYNAMIC PERFORMANCE
(2)
THD+N at f
S
(0dB)
THD+N at –60dB
Dynamic Range (EIAJ Method)
Signal-to-Noise Ratio
(3)
(EIAJ Method)
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Passband
Stop Band
Passband Ripple
Stop Band Attenuation
Delay Time
De-emphasis Error
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: I
CC
+ I
DD
+ I
CP
TEMPERATURE RANGE
Operating
Storage
NOTES: (1)
(2)
(3)
(4)
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
CONDITIONS
MIN
16
Standard/I
2
S Selectable
16/20/24 Selectable
MSB First, 2’s Comp
44.1
26.73
768f
S
(f
S
= 44.1k)
384f
S
768f
S
(f
S
= 44.1k/48k), 384f
S
(f
S
= 96k)
I
OH
= 2mA
I
OL
= 4mA
Standard Dev
f
M
= 27MHz
To Programmed Frequency
f
M
= 27MHz, C
L
= 15pF
27
33.8688
16.9344
33.8688
V
DD
– 0.4
±150
15
50
TTL
–89
–87
–31
–29
92
90
94
90
93
±1.0
±1.0
±30
0.62 x V
CA
V
CA
/2
5
0.445
0.555
±0.17
–35
11.125/f
S
–0.2
100
–0.16
4.5
5
25
5.5
27
+85
+125
+0.55
–80
dB
dB
dB
dB
dB
dB
dB
dB
dB
% of FSR
% of FSR
mV
V
PP
V
DC
kΩ
f
S
f
S
dB
dB
sec
dB
kHz
dB
VDC
mA
°C
°C
20
30
60
36.8640
36.8640
0.5
96
27.27
kHz
MHz
MHz
MHz
MHz
VDC
VDC
ps
ms
ms
%
TYP
MAX
UNITS
Bits
40
90
90
88
±3.0
±2.0
V
OUT
= V
CC
/2 at BPZ
Full Scale (–0dB)
AC Load
f = 20kHz
V
CC
= V
DD
= V
CP
f
S
= 44.1kHz
–25
–55
Sysclk transient is the maximum frequency lock time when the PLL frequency is changed.
Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
SNR is tested at Infinite Zero Detection off.
PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock.
PCM1727
SBAS077A
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