TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
instruction set
A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and
general-purpose operations, such as high-speed control. All of the′C1x devices are object-code compatible and
use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions,
permitting execution rates of more than six million instructions per second. Only infrequently used branch and
I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single
cycle and are useful for scaling data in parallel with other operations.
NOTE
The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14. An attempt to execute the
BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.
Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.
direct addressing
In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the
data memory address. This implements a paging scheme in which the first page contains 128 words, and the
second page contains up to 128 words.
indirect addressing
Indirectaddressingformsthedatamemoryaddressfromtheleast-significanteightbitsofoneofthetwoauxiliary
registers, AR0-AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary
registers can be automatically incremented or decremented and the ARP changed in parallel with the execution
of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used
with all instructions requiring data operands, except for the immediate operand instructions.
immediate addressing
Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some useful
immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary
register immediate (LARK).
instruction set summary
Table 2 lists the symbols and abbreviations used in Table 3, the instruction set summary. Table 3contains a short
description and the opcode for each ′C1x instruction. The summary is arranged according to function and
alphabetized within each functional group.
Table 2. Instruction Symbols
SYMBOL
MEANING
ACC
D
M
Accumulator
Data memory address field
Addressing mode bit
K
Immediate operand field
PA
R
S
3-bit port address field
1-bit operand field specifying auxiliary register
4-bit left-shift code
X
3-bit accumulator left-shift field
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