TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
architecture
The ′C1x DSPs use a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture,
program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle
execution. The ′C1x DSPs modification allows transfers between program and data spaces, thereby increasing
the flexibility of the device. This modification permits coefficients stored in program memory to be read into the
RAM, eliminating the need for a separate coefficient ROM.
32-bit accumulator
All ′C1x devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement
arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM
or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform
Boolean operations, providing the bit manipulation ability required of a high-speed controller. The accumulator
stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit word length. The
accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0).
Instructions are provided for storing the high- and low-order accumulator words in memory.
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16 places
on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills
the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1
or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both
shifters are useful for scaling and bit extraction.
16 × 16-bit parallel multiplier
The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction
cycle. The multiplier consists of three units: the T Register, P Register, and a multiplier array. The 16-bit T
Register stores the multiplicand, and the P Register stores the 32-bit product. Multiplier values either come from
the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast
on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and
filtering.
data and program memory
Since the ′C1x devices use a Harvard type architecture, data and program memory reside in two separate
spaces. These DSP devices have 144-or 256-words of on-chip data RAM and 1.5K- to 8K-words of on-chip
program ROM. On-chip program EPROM of 4K-words is provided in the ′E14/E15/E17 devices. An on-chip
one-time programmable 4K-word EPROM is provided in the ′P14/P15/P17 devices. The EPROM cell utilizes
standard PROM programmers and is programmed identically to a 64K CMOS EPROM (TMS27C64).
(Reference Table 1.)
program memory expansion
All′C1xdevicesexceptthe′C17/E17/LC17/P17devicesarecapableofexecutingfromoff-chipexternalmemory
at full speed for those applications requiring external program memory space. This allows for external
RAM-based systems to provide multiple functionality. The ′C17/E17/LC17/P17 devices provide no external
memory expansion. (Reference Table 1.)
microcomputer/microprocessor operating modes
All devices except the ′x17 offer two modes of operation defined by the state of the MC/MP pin: the
microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0 ). In the microcomputer mode,
on-chip ROM is mapped into the program memory space. In the microprocessor mode, all words of progam
memory are external.
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