TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C – JANUARY 1987 – REVISED JULY 1991
Table 3. TMS320C1x Instruction Set Summary
ACCUMULATOR INSTRUCTIONS
OPCODE
MNEMONIC
DESCRIPTION
NO.
CYCLES
NO.
WORDS
15
ABS
ADD
ADDH
ADDS
AND
LAC
LACK
OR
SACH
SACL
SUB
SUBC
SUBH
SUBS
XOR
ZAC
ZALH
ZALS
Absolute value of accumulator
Add to accumulator with shift
Add to high-order accumulator bits
Add to accumulator with no sign extension
AND with accumulator
Load accumulator with shift
Load accumulator immediate
OR with accumulator
Store high-order accumulator bits with shift
Store low-order accumulator bits
Subtract from accumulator with shift
Conditional subtract (for divide)
Subtract from high-order accumulator bits
Subtract from accumulator with no sign extension
Exclusive OR with accumulator
Zero accumulator
Zero accumulator and load high-order bits
Zero accumulator and load low-order bits with no sign extension
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
13
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
12
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
INSTRUCTION REGISTER
11
1
10
1
9
1
S
0
0
0
S
1
1
X
0
S
0
1
1
0
1
0
1
0
0
1
0
1
1
0
0
0
0
M
M
M
M
M
M
M
M
1
M
M
0
0
0
0
1
1
8
1
7
1
M
M
M
M
M
6
0
5
0
4
0
3
1
D
D
D
D
D
K
D
D
D
D
D
D
D
D
1
D
D
0
0
1
2
0
1
0
0
0
AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
OPCODE
MNEMONIC
DESCRIPTION
NO.
CYCLES
NO.
WORDS
15
LAR
LARK
LARP
LDP
LDPK
MAR
SAR
Load auxiliary register
Load auxiliary register immediate
Load auxiliary register pointer immediate
Load data memory page pointer
Load data memory page pointer immediate
Modify auxiliary register and pointer
Store auxiliary register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
14
0
1
1
1
1
1
0
13
1
1
1
1
1
1
1
12
1
1
0
0
0
0
1
INSTRUCTION REGISTER
11
1
0
1
1
1
1
0
10
0
0
0
1
1
0
0
9
0
0
0
1
1
0
0
8
R
R
0
1
0
0
R
1
M
0
M
M
0
0
0
0
0
0
7
M
6
5
4
3
D
K
0
D
0
D
D
0
0
K
0
0
K
2
1
0
8
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