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SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006
The TPS54317 has two internal grounds (analog and
power). Inside the TPS54317, the analog ground ties
to all of the noise sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54317, particularly at higher
output currents. Ground noise on an analog ground
plane can also cause problems with some of the
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
There should be an area of ground on the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND
pins should be tied to the PCB ground by connecting
them to the ground area under the device as shown.
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54317. Use
a separate wide trace for the analog ground signal
path. This analog ground should be used for the
voltage set point divider, timing resistor RT, slow start
capacitor and bias capacitor grounds. Connect this
trace directly to AGND (pin 1).
The PH pins should be tied together and routed to
the output inductor. Since the PH connection is the
switching node, inductor should be located very close
to the PH pins and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace
lengths.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important to
keep the loop formed by the PH pins, L
O
, C
O
and
PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pinout,
they must be routed close, but maintain as much
separation as possible while still keeping the layout
compact.
Connect the bias capacitor from the VBIAS pin to
analog ground using the isolated analog ground
trace. The bias capacitor should be as close as
possible to the VBIAS pin and analog ground . If a
slow-start capacitor or RT resistor is used, or if the
SYNC pin is used to select 350-kHz operating
frequency, connect them to this trace.
TOPSIDE GROUND AREA
INPUT
BULK
FILTER
INPUT
BYPASS
CAPACITOR
PH
PGND
PGND
NC
PH
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
PGND
PGND
VIN
PH
PH
EXPOSED
PowerPAD
AREA
PH
PH
BOOT
CAPACITOR
VOUT
Vin
VIN
VIN
VBIAS
SS/ENA
BOOT
PWRGD
COMPENSATION
NETWORK
COMP
VSENSE
AGND
SYNC
NC
RT
BIAS CAPACITOR
SLOW START
CAPACITOR
FREQUENCY SET RESISTOR
ANALOG GROUND TRACE
VIA to Ground Plane
Figure 11. TPS54317 PCB Layout
9
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