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SLVS619A – NOVEMBER 2005 – REVISED FEBRUARY 2006
PIN ASSIGNMENTS
RHF PACKAGE
(BOTTOM VIEW)
PWRGD
COMP
BOOT
PH
PH
PH
6
1
2
3
4
5
PH
7
8
9
10
11
12
VSNS
AGND
RT
NC
SYNC
24
23
22
21
20
19
18
17
16
15
14
13
PH
PH
NC
PGND
PGND
Exposed
Thermal Pad
(Pin 25)
VIN
VIN
VIN
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
COMP
PWRGD
BOOT
PH
PGND
VIN
VBIAS
SS/ENA
SYNC
RT
AGND
VSNS
NC
NO.
1
2
3
4-9
11-14
15-17
18
19
20
22
23, 25
24
10, 21
DESCRIPTION
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power good open drain output. High when VSENSE
≥
90% V
ref
, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f
s
.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Make PowerPAD connection to AGND.
Error amplifier inverting input.
Not connected internally.
SS/ENA
VBIAS
PGND
5
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