SBES014 – AUGUST 2008
................................................................................................................................................................................................
www.ti.com
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
VDD
AGND
VCC
AGND
SDI
SCLK
WRT
RDO
AGND
AGND
VCC
COB_OD
BYPR_OD
BYPP_OD
BYPM_OD
BYP_OD
NO.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TYPE
(1)
P
P
DI
DI
DI
DI
DI
DO
P
P
P
AO
AO
AO
AO
AO
AI
P
P
AO
AO
AO
P
P
AO
AO
AO
P
P
AI
AO
AO
AO
AO
AO
P
P
P
DI
DI
DI
DI
DI
DI
P
P
P
Digital supply for digital outputs (B0–B11)
Analog ground
Analog power supply
Analog ground
Serial interface data input
Serial interface data shift clock (rising edge trigger)
Serial interface data write pulse (rising edge trigger)
Serial interface register read output
Analog ground
Analog ground
Analog power supply
OB loop output voltage (odd); connect 0.1-µF capacitor between ground
Input buffer reference bypass (odd)
CDS positive reference bypass (odd); open or bypass to ground by a 0.1-µF capacitor
CDS negative reference bypass (odd); open or bypass to ground by a 0.1-µF capacitor
CDS common reference bypass (odd); bypass to ground by a 0.1-µF capacitor
CCD signal input (odd)
Analog ground
Analog supply
ADC negative reference bypass (odd); bypass to ground by a 0.1-µF capacitor
ADC common reference (odd); bypass to ground by a 0.1-µF capacitor
ADC positive reference (odd); bypass to ground by a 0.1-µF capacitor
Analog power supply
Analog ground
ADC positive reference bypass (even); bypass to ground by a 0.1-µF capacitor
ADC common reference bypass (even); bypass to ground by a 0.1-µF capacitor
ADC negative reference bypass (even); bypass to ground by a 0.1-µF capacitor
Analog power supply
Analog ground
CCD signal input (even)
CDS common reference bypass (even); bypass to ground by a 0.1-µF capacitor
CDS negative reference bypass (even); bypass to ground by a 0.1-µF capacitor
CDS positive reference bypass (even); bypass to ground by a 0.1-µF capacitor
Input buffer reference bypass (even); bypass to ground by a 0.1-µF capacitor
OB loop output voltage (even); connect 0.1-µF capacitor between ground
Analog power supply
Analog ground
Analog ground
CDS/SH mode select; high = CDS mode, low = SH mode
Chip address 1
Chip address 0
Input clamp control (active low)
Asynchronous register reset (active low)
Output enable/disable; high = high impedance, low = output enable
Analog ground
Analog power supply
Digital ground for digital outputs (B0–B11)
DESCRIPTION
PRODUCT PREVIEW
6
CCDIN_OD
AGND
VCC
REFN_OD
CM_OD
REFP_OD
VCC
AGND
REFP_EV
CM_EV
REFN_EV
VCC
AGND
CCDIN_EV
BYP_EV
BYPM_EV
BYPP_EV
BYPR_EV
COB_EV
VCC
AGND
AGND
CDS/SH_SEL
CA1
CA0
INPUTCLP
RESET
OUTENB
AGND
VCC
DGND
Product Folder Link(s):
Copyright © 2008, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
