SBES014 – AUGUST 2008
................................................................................................................................................................................................
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N
CCD
Signal
N+1
N+2
t
CKP
t
WP
SHP
(External)
t
PD
SHD
(External)
ADC_Clock
(Internal)
ECH Data
(Internal)
OCH Data
(Internal)
t
INHIBIT
SYSCLK
(External)
MUX Data
(Internal)
t
D1
MUX Clock
(Internal)
B[11:0]
(External)
N-9(EV)
t
OD
N-9(OD)
N-9(EV)
t
D2
N-9(OD)
N-8
N-8
t
ADC
t
WD
t
S
t
S
t
DP
t
CKP
N-7
N-7
t
ADC
t
CKP
N-6
N-6
PRODUCT PREVIEW
N-8(EV)
N-8(OD)
N-7(EV)
N-8(EV)
N-8(OD)
Figure 1. VSP5010 CDS Mode Timing Specifications (Even and Odd Channels) 1
TIMING CHARACTERISTICS
SYMBOL
t
CKP
t
ADC
t
WP
t
WD
t
PD
t
DP
t
S
t
INHIBIT
t
D1
t
D2
t
OD
DL
(1)
(2)
(3)
(4)
(5)
PARAMETER
Clock period
(1)
SYSCLK pulse width
SHD pulse width
SHD pulse width
SHP trailing edge to SHD leading edge
SHD trailing edge to SHP leading edge
Sampling delay
Inhibited clock period
Internal MUX clock delay 1
Internal MUX clock delay 2
(3)
(3)
(2)
MIN
32
16
6
6
8
8
TYP
MAX
UNIT
ns
ns
8.3
8.3
ns
ns
ns
ns
3.5
10
4
4
13
13
(4)
ns
ns
ns
ns
ns
ns
Output delay at data output delay = 0 ns
(4)
Output delay at data output delay = 2 ns
Data latency
(5)
Design ensured. A shipment final test is 33 ns.
Design ensured. A shipment final test is 16.7 ns.
See the
section.
Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface. See the
configuration.
Depending on an
Internal MUX clock delay
and
output delay,
latency can carry out the decrease of an increase.
8
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