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................................................................................................................................................................................................
SBES014 – AUGUST 2008
CCD
Signal
N
N+1
N+2
t
WD
SHP
(External)
t
DS
SYSCLK
(External)
ECH Data
(Internal)
OCH Data
(Internal)
MUX Data
(Internal)
t
D1
MUX Clock
(Internal)
B[11:0]
(External)
N-9(OD)
t
D2
N-8
N-7
t
ADC
t
ADC
t
S
t
CKP
t
CKP
N-6
N-8
N-7
N-6
N-9(EV)
N-8(OD)
N-8(EV)
N-7(OD)
N-9(OD)
t
OD
N-9(EV)
N-8(OD)
N-8(EV)
Figure 2. VSP5010 SH Mode Timing Specifications (Even and Odd Channels) 1
TIMING CHARACTERISTICS
SYMBOL
t
CKP
t
ADC
t
WD
t
S
t
DS
t
D1
t
D2
t
OD
DL
(1)
(2)
(3)
(4)
(5)
PARAMETER
Clock period
(1)
MIN
32
16
6
–8
TYP
MAX
UNIT
ns
ns
SYSCLK pulse width
(2)
SHD pulse width
Sampling delay
SHD trailing edge to SYSCLK leading edge
Internal MUX clock delay 1
(3)
Internal MUX clock delay 2
(3)
(4)
8.3
3.5
+6
4.5
12.5
13
17
9
ns
ns
ns
ns
ns
ns
ns
Clocks
Output delay at data output delay = 0 ns
Data latency
Output delay at data output delay = 2 ns
(5)
Design ensured. A shipment final test is 33 ns.
Design ensured. A shipment final test is 16.7 ns.
See the
section.
Load = 25 pF, data output delay = 0 ns indicates that the delay time is set by the Configuration Register of the serial interface.
Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface.
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