SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
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8.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the controller is
cycle master, this register is transmitted with the cycle start message. When the controller is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start
message is not received, the fields can continue incrementing on their own (if programmed) to maintain a
local time reference. See
for a complete description of the register contents.
OHCI register offset:
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
X
15
X
30
X
14
X
29
X
13
X
28
X
12
X
27
X
11
X
F0h
Read/Write/Update
XXXX XXXXh
26
X
10
X
25
X
9
X
24
X
8
X
23
X
7
X
22
X
6
X
21
X
5
X
20
X
4
X
19
X
3
X
18
X
2
X
17
X
1
X
16
X
0
X
Table 8-26. Isochronous Cycle Timer Register Description
BIT
31-25
24-12
11-0
FIELD NAME
cycleSeconds
cycleCount
cycleOffset
TYPE
RWU
RWU
RWU
DESCRIPTION
Cycle seconds. This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128.
Cycle count. This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000.
Cycle offset. This field counts 24.576-MHz clocks modulo 3072, that is, 125 s. If an external 8-kHz
clock configuration is being used, this field must be cleared to 000h at each tick of the external clock.
8.35 Asynchronous Request Filter High Register
The asynchronous request filter high set/clear register enables asynchronous receive requests on a
per-node basis, and handles the upper node IDs. When a packet is destined for either the physical
request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node
ID is not set to 1b in this register, the packet is not acknowledged and the request is not queued. The
node ID comparison is done if the source node is on the same bus as the controller. Nonlocal bus-sourced
packets are not acknowledged unless bit 31 in this register is set to 1b. See
for a complete
description of the register contents.
OHCI register offset:
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
0
15
0
30
0
14
0
29
0
13
0
28
0
12
0
27
0
11
0
100h set register
104 h clear register
Read/Set/Clear
0000 0000h
26
0
10
0
25
0
9
0
24
0
8
0
23
0
7
0
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
158
1394 OHCI Memory-Mapped Register Space
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