www.ti.com
SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
8.42 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the
isochronous transmit DMA contexts. The n value in the following register addresses indicates the context
number (n = 0, 1, 2, 3, ..., 7). See
for a complete description of the register contents.
OHCI register offset:
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
X
15
0
30
X
14
0
29
X
13
0
200h + (16 * n) set register
204h + (16 * n) clear register
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update,
Read/Update, Read only
XXXX X0XXh
28
X
12
X
27
X
11
0
26
X
10
0
25
X
9
0
24
X
8
0
23
X
7
X
22
X
6
X
21
X
5
X
20
X
4
X
19
X
3
X
18
X
2
X
(1)
17
X
1
X
16
X
0
X
Table 8-33. Isochronous Transmit Context Control Register Description
BIT
31
FIELD NAME
cycleMatchEnable
TYPE
RSCU
DESCRIPTION
When bit 31 is set to 1b, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 30-16). The cycleMatch field (bits 30-16) must match the low-order two bits of
cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received
immediately before isochronous transmission begins. Since the isochronous transmit DMA
controller may work ahead, the processing of the first descriptor block may begin slightly in
advance of the actual cycle in which the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the 1394 Open Host Controller Interface Specification. Once the context has
become active, hardware clears this bit.
30-16
cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous
cycle timer register at OHCI offset F0h (see
cycleSeconds field (bits 31-25) and
the cycleCount field (bits 24-12). If bit 31 (cycleMatchEnable) is set to 1b, this isochronous
transmit DMA context becomes enabled for transmits when the low-order two bits of the
isochronous cycle timer register at OHCI offset F0h cycleSeconds field (bits 31-25) and the
cycleCount field (bits 24-12) value equal this field (cycleMatch) value.
Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by
software to stop descriptor processing. The controller changes this bit only on a system
(hardware) or software reset.
Reserved. Bits 14 and 13 return 00b when read.
Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing.
The controller clears this bit on every descriptor fetch.
The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when
software clears bit 15 (run) to 0b.
The controller sets bit 10 to 1b when it is processing descriptors.
Reserved. Bits 9-5 return 00000b when read.
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible
values are ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
15
run
RSC
14-13
12
11
10
9-5
4-0
(1)
RSVD
wake
dead
active
RSVD
eent code
R
RSU
RU
RU
R
RU
On an overflow for each running context, the isochronous transmit DMA supports up to seven cycle skips when the following are true:
• Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1b.
• Bits 4-0 (eventcode field) in either the isochronous transmit or receive context control register are set to evt_timeout.
• Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see
) is set to 1b.
Copyright © 2009–2010, Texas Instruments Incorporated
1394 OHCI Memory-Mapped Register Space
Product Folder Link(s):
167
TI [ TEXAS INSTRUMENTS ]
