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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
9.2
Isochronous Receive Digital Video Enhancements
The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize
1394 DV data that is received in the correct order to DV frame-sized data buffers described by several
INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1). This is
accomplished by waiting for the start-of-frame packet in a DV stream before transferring the received
isochronous stream into the memory buffer described by the INPUT_MORE descriptors. This can improve
the DV capture application performance by reducing the amount of processing overhead required to strip
the CIP header and copy the received packets into frame-sized buffers.
The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and
second byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet.
9.3
Isochronous Receive Digital Video Enhancement Registers
The isochronous receive digital video enhancement registers enable the DV enhancements in the
controller. The bits in these registers may only be modified when both the active (bit 10) and run (bit 15)
bits of the corresponding context control register are 00b. See
for a complete description of the
register contents.
TI extension register offset:
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
0
15
0
30
0
14
0
29
0
13
0
28
0
12
0
27
0
11
0
A80h set register
A84h clear register
Read/Set/Clear, Read only
0000 0000h
26
0
10
0
25
0
9
0
24
0
8
0
23
0
7
0
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
Table 9-2. Isochronous Receive Digital Video Enhancement Registers Description
BIT
31-14
13
FIELD NAME
RSVD
DV_Branch3
TYPE
R
RSC
DESCRIPTION
Reserved. Bits 31-14 return 00 0000 0000 0000 0000b when read.
When bit 13 is set to 1b, the isochronous receive context 3 synchronizes reception to the DV frame
start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by
frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12
(CIP_Strip3) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 460h/464h (see
is cleared to 0b.
When bit 12 is set to 1b, the isochronous receive context 3 strips the first two quadlets of payload.
This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control
register at OHCI offset 460h/464h (see
is cleared to 0b.
Reserved. Bits 11 and 10 return 00b when read.
When bit 9 is set to 1b, the isochronous receive context 2 synchronizes reception to the DV frame
start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by
frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8
(CIP_Strip2) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 440h/444h (see
is cleared to 0b.
When bit 8 is set to 1b, the isochronous receive context 2 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 440h/444h (see
is cleared to 0b.
Reserved. Bits 7 and 6 return 00b when read.
When bit 5 is set to 1b, the isochronous receive context 1 synchronizes reception to the DV frame
start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by
frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4
(CIP_Strip1) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see
is cleared to 0b.
12
CIP_Strip3
RSC
11-10
9
RSVD
DV_Branch2
R
RSC
8
CIP_Strip2
RSC
7-6
5
RSVD
DV_Branch1
R
TSC
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1394 OHCI Memory-Mapped TI Extension Register Space
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