SCPS216A – JULY 2009 – REVISED FEBRAURY 2010
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Table 9-2. Isochronous Receive Digital Video Enhancement Registers Description (continued)
BIT
4
FIELD NAME
CIP_Strip1
TYPE
RSC
DESCRIPTION
When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 420h/424h (see
is cleared to 0b.
Reserved. Bits 3 and 2 return 00b when read.
When bit 1 is set to 1b, the isochronous receive context 0 synchronizes reception to the DV frame
start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by frameBranch
a DV frame start tag is received out of place. This bit is only interpreted when bit 0 (CIP_Strip0) is set
to 1b and bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset
400h/404h (see
is cleared to 0b.
When bit 0 is set to 1b, the isochronous receive context 0 strips the first two quadlets of payload. This
bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at
OHCI offset 400h/404h (see
is cleared to 0b.
3-2
1
RSVD
DV_Branch0
R
RSC
0
CIP_Strip0
RSC
9.4
Link Enhancement Control Registers
These registers are a memory-mapped set/clear registers that are an alias of the link enhancement control
register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be
initialized by a serial EEPROM, if one is present, as noted in the following bit descriptions. If the bits are to
be initialized by software, the bits must be initialized prior to setting bit 19 (LPS) in the host controller
control register at OHCI offset 50h/54h (see
See
for a complete description of
the register contents.
TI extension register offset:
Register type:
Default value:
BIT NUMBER
RESET STATE
BIT NUMBER
RESET STATE
31
0
15
0
30
0
14
0
29
0
13
0
28
0
12
1
A88h set register
A8Ch clear register
Read/Set/Clear, Read only
0000 0000h
27
0
11
0
26
0
10
0
25
0
9
0
24
0
8
0
23
0
7
0
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
Table 9-3. Link Enhancement Control Registers Description
BIT
31-16
15
(1)
FIELD NAME
RSVD
dis_at_pipleline
RSVD
TYPE
R
RW
RW
DESCRIPTION
Reserved. Bits 31-16 return 0000h when read.
Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default
value for this bit is 0b.
Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.
14
(1)
(1)
This bit is reset by PERST or FRST.
174
1394 OHCI Memory-Mapped TI Extension Register Space
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