VIS
DC Characteristics ; 3.3 - Volt Version (cont.)
(T
a
= 0 to 70°C, V
CC
= + 3.3V
±
10%, V
SS
= 0V)
Parameter
Input leakage
current
Output leakage
current
Symbol
I
LI
I
LO
Test Conditions
0V
≤
Vin
≤
V
CC
+ 0.3V
0V
≤
Vout
≤
V
C C
+ 0.3V
Dout = Disable
l
OH
= -2mA
VG26(V)(S)17400E
4,194,304 x 4 - Bit
CMOS Dynamic RAM
VG26 (V) (S) 17400E
Unit Notes
-5
-6
Min Max Min Max
-5
5
-5
5
µA
-5
5
-5
5
µA
Output high
V
OH
2.4
- 2.4
- V
voltage
Output low
V
OL
l
OL
= + 2mA
-
0.4
-
0.4 V
voltage
Notes :
1. l
CC
is specified as an average current. It depends on output loading condition and cycle rate when
the device is selected. l
CC
max is specified at the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. For l
CC4
, address can be changed once or less within one Fast page mode cycle time.
Document : 1G5-0142
Rev.1
Page 9
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
