WM8216
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
NAME
RSMP
MCLK
DGND
SEN
DVDD2
SDI
SCK
NC
NC
TYPE
Digital input
Digital input
Supply
Digital input
Supply
Digital input
Digital input
No connect
No connect
DESCRIPTION
Reset sample pulse (when CDS=1) or clamp control (CDS=0)
Master (ADC) clock. This clock determines the ADC conversion rate.
Digital ground.
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Serial data input.
Serial clock.
No internal connection.
No internal connection.
Production Data
Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel
format.
10
11
12
13
14
15
16
17
18
19
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]/SDO
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d0 (LSB)
d1
d2
d3
d4
d5
d6
d7
d8
d9 (MSB)
Alternatively, pin OP[9]/SDO may be used to output register read-back data when
OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
20
21
22
23
24
25
AVDD
AGND1
VRB
VRT
VRX
VRLC/VBIAS
Supply
Supply
Analogue output
Analogue output
Analogue output
Analogue I/O
Analogue supply. This must be operated at the same potential as DVDD1.
Analogue ground.
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Used for test purposes only. Do not externally connect – leave this pin floating.
Even channel input video.
Odd channel input video.
Analogue ground.
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control. All digital outputs set to high-impedance state when input pin
OEB=1 or register bit OPD=1.
Video sample pulse.
26
27
28
29
30
31
32
TEST
EINP
OINP
AGND2
DVDD1
OEB
VSMP
Analogue I/O
Analogue input
Analogue input
Supply
Supply
Digital input
Digital input
w
PD Rev 4.0 March 2007
4
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
