WM8216
INPUT VIDEO SAMPLING
Production Data
t
RSD
t
RSFVSR
t
MF1RS
t
VSD
t
MRVSR
t
PR2
t
MFVSF
t
VSFMR
t
PD
t
MCLKL
E
t
MCLKH
O
E
t
PER
O
E
O
E
n-5
n-4
n-3
n-2
n-1
Figure 1 Two-channel CDS Operation (CDS=1)
Input
Video
t
RSD
PIXEL n
t
RSFVSR
t
MF1RS
t
PR1
RSMP
t
VSD
t
VSFMR
VSMP
t
MRVSR
t
MFVSF
t
PD
MCLK
Output
Data
OP[9:0]
t
MCLKH
t
MCLKL
t
PER
n-8
Figure 2 One-channel CDS Operation (CDS=1)
n-7
n-6
n-5
Notes:
1.
2.
3.
4.
5.
6.
7.
The relationship between input video signal and sample points is controlled by VSMP and RSMP.
When VSMP is high the input video signal is connected to the Video sampling capacitors.
When RSMP is high the input video signal is connected to the Reset sampling capacitors.
RSMP must not go high before the first falling edge of MCLK after VSMP goes low.
It is required that the falling edge of VSMP should occur before the rising edge of MCLK.
In 1-channel CDS mode it is not possible to have equally spaced Video and Reset sample points with a 45MHz
MCLK.
Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.
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PD Rev 4.0 March 2007
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
