WM8216
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, T
A
= 25°C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate
Full-scale input voltage range
(see Note 1)
LOWREFS=0, Max Gain
LOWREFS=0, Min Gain
LOWREFS=1, Max Gain
LOWREFS=1, Min Gain
Input signal limits (see Note 2)
Input capacitance
Input switching impedance
Full-scale transition error
Zero-scale transition error
Differential non-linearity
Integral non-linearity
Channel to channel gain matching
Output noise
References
Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
RLCDAC
RLCDAC
Notes:
1.
2.
Full-scale input voltage
denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
Input signal limits
are the limits within which the full-scale input voltage signal must lie.
PD Rev 4.0 March 2007
6
V
RLCSTEP
V
RLCSTEP
V
RLCBOT
V
RLCBOT
V
RLCTOP
V
RLCTOP
DNL
INL
AVDD=3.3V
LOWREFS = 0
AVDD=3.3V
LOWREFS = 0
AVDD=3.3V
LOWREFS = 0
-0.5
+/-0.5
VRLC = 0 to AVDD
4
0.173
0.11
0.4
0.4
3.0
2.05
+0.5
45
2
2
1
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
LSB
LSB
VRT
VRB
VRX
V
RTB
LOWREFS=0
LOWREFS=1
0.9
LOWREFS=0
LOWREFS=1
LOWREFS=0
LOWREFS=1
1.95
0.95
2.05
1.85
1.05
1.25
1.25
1.0
0.6
1
1.10
2.25
1.25
V
V
V
V
V
V
V
Ω
Min Gain
Max Gain
DNL
INL
Gain = 0dB;
PGA[7:0] = 4B(hex)
Gain = 0dB;
PGA[7:0] = 4B(hex)
V
IN
AGND-0.3
10
45
20
20
0.75
2
1%
0.2
2.15
60
0.25
3.03
0.15
1.82
AVDD+0.3
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
pF
Ω
mV
mV
LSB
LSB
%
LSB rms
LSB rms
w