X28VC256
PIN DESCRIPTIONS
Addresses (A
0
–A
14
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28VC256 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28VC256.
PIN NAMES
Symbol
A
0
–A
14
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
PIN CONFIGURATION
PGA
I/O1
I/O2
I/O3
I/O6
I/O5
12
13
15
18
17
I/O0
A0
11
10
A1
A3
A5
A2
A4
A12
VSS
I/O4
I/O7
14
16
19
CE
20
OE
22
VCC
A9
28
24
A14
WE
27
A10
21
A11
23
A8
25
A13
26
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3869 PGM T01
9
8
7
6
5
2
4
A6
3
A7
1
3869 FHD F04
X28VC256
(BOTTOM VIEW)
FUNCTIONAL DIAGRAM
X BUFFERS
LATCHES AND
DECODER
A0–A14
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
256K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
3869 FHD F01
CONTROL
LOGIC AND
TIMING
3869 FHD F01
2
XICOR [ XICOR INC. ]
