R
Virtex-II Platform FPGAs: Functional Description
Table 2:
Supported Differential Signal I/O Standards
I/O Standard
LVPECL_33
LDT_25
LVDS_33
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
Logic Resources
IOB blocks include six storage elements, as shown in
IOB
DDR mux
Reg
OCK1
Reg
ICK1
Reg
OCK2
3-State
Reg
ICK2
DDR mux
Reg
Input
Output
V
CCO
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
Input
V
CCO
N/R
(1)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Input
V
REF
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Output
V
OD
0.490 - 1.220
0.500 - 0.700
0.250 - 0.400
0.250 - 0.400
0.440 - 0.820
0.440 - 0.820
0.250 - 0.450
0.500 - 0.700
Notes:
1.
N/R = no requirement.
Table 3:
Supported DCI I/O Standards
I/O
Standard
LVDCI_33
(1)
LVDCI_DV2_33
(1)
LVDCI_25
(1)
LVDCI_DV2_25
(1)
LVDCI_18
(1)
LVDCI_DV2_18
(1)
LVDCI_15
(1)
LVDCI_DV2_15
(1)
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI
(3)
SSTL18_II_DCI
SSTL2_I_DCI
(2)
SSTL2_II_DCI
(2)
SSTL3_I_DCI
(2)
SSTL3_II_DCI
(2)
LVDS_25_DCI
LVDSEXT_25_DCI
Output
V
CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
Input
V
CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
2.5
2.5
Input
V
REF
N/R
(4)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.75
0.75
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
1.25
1.25
1.5
1.5
N/R
N/R
Termination
Type
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Split
Split
Single
Single
Split
Split
Single
Single
Split
Split
Split
Split
Split
Split
Split
Split
OCK1
PAD
Reg
OCK2
Output
DS031_29_100900
Figure 2:
Virtex-II IOB Block
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
There are two input, output,
and 3-state data signals, each being alternately clocked out.
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half of
the reference resistors.
2. These are SSTL compatible.
3.
4.
SSTL18_I is not a JEDEC-supported standard.
N/R = no requirement.
DS031-2 (v3.5) November 5, 2007
Product Specification
Module 2 of 4
2
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