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Virtex-II Platform FPGAs:
Functional Description
Product Specification
DS031-2 (v3.5) November 5, 2007
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II™ I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Table 1:
Supported Single-Ended I/O Standards
IOSTANDARD
Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
IOB
PAD4
Differential Pair
IOB
PAD3
Switch
Matrix
IOB
PAD2
Differential Pair
IOB
PAD1
DS031_30_101600
Output
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
3.3
Input
V
CCO
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
Note (1)
Note (1)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Input
V
REF
N/R
(3)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.8
1.0
0.75
0.75
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
1.25
1.25
1.5
1.5
1.32
Board
Termination
Voltage (V
TT
)
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.25
1.25
1.5
1.5
N/R
PCI66_3
PCI-X
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
Figure 1:
Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
SSTL18_I
(2)
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP-2X/AGP
Notes:
1.
2.
3.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
CCINT
= 1.5V),
output driver supply voltage (V
CCO
) is dependent on the I/O
standard (see
and
An auxiliary supply volt-
age (V
CCAUX
= 3.3 V) is required, regardless of the I/O
standard used. For exact supply voltage absolute maximum
ratings, see
in Module 3.
All of the user IOBs have fixed-clamp diodes to V
CCO
and to
ground. As outputs, these IOBs are not compatible or com-
pliant with 5V I/O standards. As inputs, these IOBs are not
normally 5V tolerant, but can be used with 5V I/O standards
when external current-limiting resistors are used. For more
details, see the “5V Tolerant I/Os“ Tech Topic at
www.xil-
inx.com
.
lists supported I/O standards with Digitally Con-
trolled Impedance. See
V
CCO
of GTL or GTLP should not be lower than the termination
voltage or the voltage seen at the I/O pad. Example: If the pin High
level is 1.5V, connect V
CCO
to 1.5V.
SSTL18_I is not a JEDEC-supported standard.
N/R = no requirement.
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trademarks are the property of their respective owners.
DS031-2 (v3.5) November 5, 2007
Product Specification
Module 2 of 4
1
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