R
Spartan-3 FPGA Family: Functional Description
T
T1
D
CE
CK
SR
Q
TFF1
REV
DDR
MUX
TCE
T2
D
CE
CK
SR
Q
TFF2
REV
Three-state Path
O1
D
CE
Q
OFF1
V
CCO
OTCLK1
CK
SR
Pull-Up
REV
DDR
MUX
ESD
I/O
Pin
OCE
O2
D
CE
OTCLK2
CK
SR
Q
OFF2
Program-
mable
Output
Driver
DCI
Pull-
Down
ESD
REV
Keeper
Latch
Output Path
I
IQ1
D
CE
ICLK1
ICE
CK
SR
Q
IFF1
Fixed
Delay
Single-ended Standards
using VREF
V
REF
Pin
REV
Differential Standards
IQ2
D
CE
ICLK2
SR
REV
Input Path
Note:
All IOB signals originating from the FPGA's internal logic have an optional polarity inverter.
DS099-2_01_112905
Fixed
Delay
LVCMOS, LVTTL, PCI
Q
IFF2
I/O Pin
from
Adjacent
IOB
CK
SR
REV
Figure 5:
Simplified IOB Diagram
DS099-2 (v2.4) June 25, 2008
Product Specification
13
XILINX [ XILINX, INC ]
