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Spartan-3 FPGA Family:
Functional Description
0
DS099-2 (v2.4) June 25, 2008
Product Specification
For specific hardware examples, please see the Spartan-3
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
•
•
Spartan-3 FPGA Starter Kit Board Page
UG130: Spartan-3 FPGA Starter Kit User Guide
New Spartan-3 Generation Design
Documentation Available
The functionality of the Spartan
®
-3 FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
•
UG331: Spartan-3 Generation FPGA User Guide
- Clocking Resources
- Digital Clock Managers (DCMs)
- Block RAM
- Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
- I/O Resources
- Embedded Multiplier Blocks
- Programmable Interconnect
- ISE
®
Software Design Tools
- IP Cores
- Embedded Processing and Control Solutions
- Pin Types and Package Overview
- Package Drawings
- Powering FPGAs
UG332: Spartan-3 Generation Configuration User
Guide
- Configuration Overview
·
Configuration Pins and Behavior
·
Bitstream Sizes
- Detailed Descriptions by Mode
·
Master Serial Mode using Xilinx Platform Flash
PROM
·
Slave Parallel (SelectMAP) using a Processor
·
Slave Serial using a Processor
·
JTAG Mode
- ISE iMPACT Programming Examples
Create a Xilinx MySupport user account and sign up to
receive automatic E-mail notification whenever this data
sheet or the associated user guides are updated.
•
Sign Up for Alerts on Xilinx MySupport
•
© 2004-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-2 (v2.4) June 25, 2008
Product Specification
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XILINX [ XILINX, INC ]
