eZ80F91 ASSP
Product Specification
118
Basic Timer Operation
Basic timer operation is controlled by a timer control register and a programmable reload
value. The CPU uses the control register to setup the prescaling, the input clock source,
the end-of-count behavior, and to start the timer. The 16-bit reload value is used to deter-
mine the duration of the timer’s count before either halting or reloading.
After choosing a timer period and writing the appropriate values to the reload registers, the
CPU must set the timer enable bit (TMRx_CTL[TIM_EN]) by allowing the count to
begin. The reload bit (TMRx_CTL[RLD]) must also be asserted so that the timer counts
down from the reload value rather than from 0000h. On the system clock cycle, after the
assertion of the reload bit, the timer loads with the 16-bit reload value and begins counting
down. The reload bit is automatically cleared after the loading operation. The timer is
enabled and reloaded on the same cycle; however, the timer does not require disabling to
reload and reloading is performed at any time. It is also possible to halt the timer by deas-
serting the timer enable bit and resuming the count at a later time from the same point by
reasserting the bit.
Reading the Current Count Value
The CPU reads the current count value when the timer is running. Because the count is a
16-bit value, the hardware latches the value of the upper byte into temporary storage when
the lower byte is read. This value in temporary storage is the value returned when the
upper byte is read. Therefore, the software must read the lower byte first. If it attempts to
read the upper byte first, it does not obtain the current upper byte of the count. Instead, it
obtains the last latched value. This read operation does not affect timer operation.
Setting Timer Duration
There are three factors to consider while determining Programmable Reload Timer dura-
tion: clock frequency, clock divider ratio, and initial count value. Minimum duration of the
timer is achieved by loading 0001h. Maximum duration is achieved by loading 0000h,
because the timer first rolls over to FFFFh and then continues counting down to 0000h
before the end-of-count is signaled. Depending on the TMRx_CTL[CLK_SEL] bits of the
control register, the clock is either the system clock, or an on-chip RC oscillator output or
an input from a pin.
The time-out period of the timer is returned by the following equation:
Clock Divider Ratio x Reload Value
Time-Out Period =
System Clock Frequency
To calculate the time-out period with the above equation while using an initial value of
0000h, enter a reload value of 65536 (FFFFh+ 1).
PS027004-0613
P R E L I M I N A R Y
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
