eZ80F91 ASSP
Product Specification
121
deactivated by a CPU read of the timer interrupt identification register, TMRx_IIR. All
bits in that register are reset by the read.
The response of the CPU to this interrupt service request is a function of the CPU’s inter-
rupt enable flag, IEF1. For more information about this flag, refer to the
available for free download from the Zilog website.
Timer Input Source Selection
Timers 0–3 features programmable input source selection. By default, the input is taken
from the eZ80F91’s system clock. The timers also use the Real-Time Clock source (50,
60, or 32768THz) as their clock sources. The input source for these timers is set using the
timer control register. (TMRx_CTL[CLK_SEL])
Timer Output
The timer count is directed to the GPIO output pins, if required. To enable the Timer Out-
put feature, the GPIO port pin must be configured as an output and for alternate functions.
The GPIO output pin toggles each time the timer reaches its end-of-count value. In CON-
TINUOUS Mode operation, enabling the Timer Output feature results in a Timer Output
signal period which is twice the timer time-out period. Examples of Timer Output opera-
tion are shown in Figure 29 and Table 52. The initial value for the timer output is zero.
Logic to support timer output exists in all timers; but for the eZ80F91 device, only Timer
0 and 2 route the actual timer output to the pins. Because Timer 3 uses the T
OUT
pins for
PWMxN signals, the timer outputs are not available when using complementary PWM
outputs. See Table 52 for details.
System Clock
Clock Enable
TMR3_CTL Write
(Timer Enable)
T3 Count
Timer Out
(internal)
Timer Out
(at pad)
0
4
3
2
1
4
3
2
1
Figure 29. Example: PRT Timer Output Operation
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
