eZ80F91 ASSP
Product Specification
122
Table 52. Example: PRT Timer Out Parameters
Parameter
Timer Enable
Reload
Prescaler Divider = 4
CONTINUOUS Mode
Timer Reload Value
Control Register(s)
TMR
x
_CTL[TIM_EN]
TMR
x
_CTL[RLD]
TMR
x
_CTL[CLK_DIV]
TMR
x
_CTL[TIM_CONT]
{TMR
x
_RR_H, TMRx_RR_L}
Value
1
1
00b
1
0003h
Break Point Halting
When the eZ80F91 device is running in DEBUG Mode, encountering a break point causes
all CPU functions to halt. However, the timers keep running. This instance makes debug-
ging timer-related software much more difficult. Therefore, the control register contains a
BRK_STP bit. Setting this bit causes the count value to be held during debug break points.
Specialty Timer Modes
The features described above are common to all timers in the eZ80F91 device. In addition
to these common features, some of the timers have additional functionality.
The following bullets list the special features for each timer:
•
•
•
•
Timer 0
–
No special functions
Timer 1
–
One event counter (EC0)
–
Two input captures (IC0 and IC1)
Timer 2
–
One event counter (EC1)
Timer 3
–
Two input captures (IC2 and IC3)
–
Four output compares (OC0, OC1, OC2, and OC3)
–
Four PWM outputs (PWM0, PWM1, PWM2, and PWM3)
Timer 3 consists of three specialty modes. Each of these modes are enabled using bits in
their respective control registers (TMR3_CAP_CTL, TMR3_OC_CTL1,
TMR3_PWM_CTL1). When PWM Mode is enabled, the OUTPUT COMPARE and
INPUT CAPTURE modes are not available. This instance is due to address space sharing
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
