Z
ILOG
Z5380 SCSI
FUNCTIONAL DESCRIPTION (Continued)
D7
D0
For send operations, the End of DMA bit is set when the
DMAfinishesitstransfers,buttheSCSItransfermaystillbe
in progress. If connected as a Target, /REQ and /ACK
should be sampled until both are False. If connected as an
Initiator, a phase change interrupt is used to signal the
completion of the previous phase. It is possible for the
Target to request additional data for the same phase. In
this case, a phase change will not occur and both /REQ
and/ACKaresampledtodeterminewhenthelastbytewas
transferred.
X
X
X
X
X
X
X
X
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
SCSI Bus Reset Interrupt
The Z5380 generates an interrupt when the /RST signal
transitions to True. The device releases all bus signals
withinabus-cleardelayofthistransition.Thisinterruptalso
occurs after setting the Assert /RST bit (Initiator Command
Register, bit 7). This interrupt cannot be disabled. (Note:
/RST is not latched in bit 7 of the Current SCSI Bus Status
Register and is not active when this port is read. For this
case, the Bus Reset interrupt is determined by default.)
Figure 19. Current SCSI Bus Status Register
Parity Error Interrupt
An Interrupt is generated for a received parity error if the
Enable Parity Check (bit 5) and the Enable Parity Interrupt
(bit 4) bits are set (1) in the Mode Register. Parity is
checked during a read of the Current SCSI Data Register
and during a DMA receive operation. A parity error can be
detected without generating an interrupt by disabling the
Enable Parity Interrupt bit and checking the Parity Error
flag (Bus and Status Register, bit 5).
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
18 and 19, respectively.
D7
D0
0
X
0
1
X
0
X
X
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
20 and 21, respectively.
/ACK
/ATN
Busy Error
D7
D0
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
0
X
1
1
1
0
X
X
/ACK
/ATN
Busy Error
Phase Match
Interrupt Request Active
Parity Error
DMA Request
End of DMA
Figure 18. Bus and Status Register
Figure 20. Bus and Status Register
12
PS97SCC0100
PS009101-0201
ZILOG [ ZILOG, INC. ]
