Z
ILOG
Z5380 SCSI
D7
D0
D7
D0
0
0
0
1
0
0
X
0
0
1
1
X
X
X
0
X
/ACK
/DBP
/SEL
I//O
/ATN
Busy Error
Phase Match
C//D
Interrupt Request Active
Parity Error
/MSG
/REQ
/BSY
/RST
DMA Request
End of DMA
Figure 21. Current SCSI Bus Status Register
Figure 22. Bus and Status Register
D7
D0
Bus Phase Mismatch Interrupt
0
1
X
X
X
X
0
X
The SCSI phase lines are comprised of the signals I//O,
C//D, and /MSG. These signals are compared with the
corresponding bits in the Target Command Register: As-
sert I//O (bit 0), Assert C//D (bit 1), and Assert /MSG (bit 2).
The comparison occurs continually and is reflected in the
PhaseMatchbit(bit3)oftheBusandStatusRegister. Ifthe
DMA Mode bit (Mode Register, bit 1) is active and a phase
mismatch occurs when /REQ transitions from False to
True, an interrupt (IRQ) is generated.
/DBP
/SEL
I//O
C//D
/MSG
/REQ
/BSY
/RST
A phase mismatch prevents the recognition of /REQ and
removes the chip from the bus during an Initiator send
operation (/DB7-/DB0 and /DBP will not be driven even
through the Assert Data Bus bit (Initiator Command Reg-
ister, bit 0) is active). This may be disabled by resetting the
DMAModebit(Note:Itispossibleforthisinterrupttooccur
whenconnectedasaTargetifanotherdeviceisdrivingthe
phase lines to a different state).
Figure 23. Current SCSI Bus Status Register
Loss of BSY Interrupt
If the Monitor Busy bit (bit 2) in the Mode Register is active,
an interrupt is generated if the BSY signal goes False for at
least a bus-settle delay. This interrupt is disabled by
resetting the Monitor Busy bit. Register values are dis-
played in Figures 24 and 25.
The proper values for the Bus and Status Register and the
Current SCSI Bus Status Register are displayed in Figures
22 and 23, respectively.
13
PS97SCC0100
PS009101-0201
ZILOG [ ZILOG, INC. ]
