ACPL-332J应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

ACPL-332J

2.5 Amp Output Current IGBT Gate Driver Optocoupler

with Integrated (V ) Desaturation Detection, UVLO

CE

Fault Status Feedback and Active Miller Clamping

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

Features

The ACPL-332J is an advanced 2.5 A output current, easy-

ꢀ Under Voltage Lock-Out Protection (UVLO) with

to-use, intelligent gate driver which makes IGBT V fault

Hysteresis

CE

protection compact, aﬀordable, and easy-to implement.

ꢀ Desaturation Detection

ꢀ Miller Clamping

Features such as integrated

V

detection, under

CE

voltage lockout (UVLO), “soft” IGBT turn-oﬀ, isolated

open collector fault feedback and active Miller clamping

provide maximum design ﬂexibility and circuit protec-

tion.

ꢀ Open Collector Isolated fault feedback

ꢀ

“Soft”IGBT Turn-oﬀ

ꢀ Fault Reset by next LED turn-on (low to high) after

The ACPL-332J contains a GaAsP LED. The LED is optically

coupled to an integrated circuit with a power output

stage. ACPL-332J is ideally suited for driving power IGBTs

and MOSFETs used in motor control inverter applications.

The voltage and current supplied by these optocouplers

make them ideally suited for directly driving IGBTs with

ratings up to 1200 V and 150 A. For IGBTs with higher

ratings, the ACPL-332J can be used to drive a discrete

power stage which drives the IGBT gate. The ACPL-332J

fault mute period

ꢀ Available in SO-16 package

ꢀ Safety approvals: UL approved, 5000 V

for 1

RMS

minute, CSA approved, IEC/EN/DIN-EN 60747-5-2

approved V

= 1230 V

IORM

PEAK

Speciﬁcations

ꢀ 2.5 A maximum peak output current

ꢀ 2.0 A minimum peak output current

has an insulation voltage of V

= 1230 V

.

IORM

PEAK

ꢀ 250 ns maximum propagation delay over temperature

Block Diagram

range

13

V_CC2

ꢀ 100 ns maximum pulse width distortion (PWD)

UVLO

6, 7

5, 8

D

R

I

V

E

R

ꢀ 15 kV/μs minimum common mode rejection (CMR) at

ANODE

11

V

= 1500 V

CM

V_OUT

DESAT

CATHODE

LED1

ꢀ I

< 5 mA maximum supply current

CC(max)

14

DESAT

ꢀ Wide V operating range: 15 V to 30 V over

CC

9, 12

temperature range

V_EE

SHIELD

LED2

ꢀ 1.7 A Miller Clamp. Clamp pin short to V if not used

EE

V_CLAMP

2

3

ꢀ Wide operating temperature range: –40°C to 105°C

10

16

V_CC1

V_CLAMP

V_E

Applications

FAULT

ꢀ Isolated IGBT/Power MOSFET gate drive

ꢀ AC and brushless DC motor drives

1, 4

15

V_S

V_LED

SHIELD

ꢀ Industrial inverters and Uninterruptible Power Supply

(UPS)

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation which may be induced by ESD.

Pin Description

1

Symbol

V_S

Description

Input Ground

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

2

V_CC1

FAULT

Positive input supply voltage. (3.3 V to 5.5 V)

3

Fault output. FAULT changes from a high impedance state

to a logic low output within 5 μs of the voltage on the

DESAT pin exceeding an internal reference voltage of 7 V.

FAULT output is an open collector which allows the FAULT

outputs from all ACPL-332J in a circuit to be connected

together in a “wired OR” forming a single fault bus for inter-

facing directly to the micro-controller.

V_CC1

FAULT

V_S

DESAT 14

V_CC213

4

V_S

Input Ground

CATHODE

ANODE

CATHODE

V_EE12

5

CATHODE Cathode

6

ANODE

Anode

V_OUT11

V_CLAMP10

7

8

CATHODE Cathode

9

V_EE

Output supply voltage.

V_EE

9

10

11

12

13

14

V_CLAMP

V_OUT

V_EE

Miller clamp

Gate drive voltage output

Output supply voltage.

Positive output supply voltage

V_CC2

DESAT

Desaturation voltage input. When the voltage on DESAT

exceeds an internal reference voltage of 6.5 V while the

IGBT is on, FAULT output is changed from a high impedance

state to a logic low state within 5 μs.

15

16

V_LED

LED anode. This pin must be left unconnected for guaran-

teed data sheet performance. (For optical coupling testing

only)

V_E

Common (IGBT emitter) output supply voltage.

Ordering Information

ACPL-332J is UL Recognized with 5000 Vrms for 1 minute per UL1577.

Option

Surface

Mount

IEC/EN/DIN EN

60747-5-2

Part number

RoHS Compliant

-000E

Package

Tape& Reel

Quantity

ACPL-332J

SO-16

X

45 per tube

850 per reel

-500E

X

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

ACPL-332J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN

60747-5-2 Safety Approval in RoHS compliant.

Example 2:

ACPL-332J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-

2 Safety Approval and RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and

RoHS compliant option will use ‘-XXXE‘.

2

Package Outline Drawings

ACPL-332J 16-Lead Surface Mount Package

0.018

0.050

LAND PATTERN RECOMMENDATION

(0.457ꢀ

(1.270ꢀ

16 15 14 13 12 11 10

9

TYPE NUMBER

DATE CODE

A 332J

YYWW

0.458 (11.63ꢀ

0.295 0.010

(7.493 0.254ꢀ

0.085 (2.16ꢀ

1

2

3

4

5

6

7

8

0.406 0.10

0.025 (0.64ꢀ

(10.312 0.254ꢀ

0.345 0.010

ALL LEADS

9°

(8.763 0.254ꢀ

TO BE

COPLANAR

0.002

0.138 0.005

0.018

0- 8°

0.025 MIN.

0.008 0.003

(3.505 0.127ꢀ

(0.457ꢀ

(0.203 0.076ꢀ

STANDOFF

0.408 0.010

(10.363 0.254ꢀ

Dimensions in inches (millimeters)

Notes: Initial and continued variation in the color of the ACPL-332J’s white mold compound is normal and does note aﬀect device performance or

reliability.

Floating Lead Protrusion is 0.25 mm (10 mils) max.

Recommended Pb-Free IR Proﬁle

Recommended reﬂow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

3

Regulatory Information

The ACPL-332J is approved by the following organizations:

IEC/EN/DIN EN 60747-5-2

UL

Approval under:

Approval under UL 1577, component recognition

IEC 60747-5-5 :1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01

program up to V = 5000 V . File E55361.

ISO

RMS

CSA

Approval under CSA Component Acceptance Notice #5,

File CA 88324.

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description

Symbol

Characteristic

Unit

Installation classiﬁcation per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 150 V_rms

for rated mains voltage ≤ 300 V_rms

for rated mains voltage ≤ 600 V_rms

for rated mains voltage ≤ 1000V_rms

I – IV

I – III

Climatic Classiﬁcation

55/100/21

2

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

V_IORM

V_PR

1230

2306

V_peak

Input to Output Test Voltage, Method b**,

V_IORMx 1.875=V_PR, 100% Production Test with t_m=1 sec, Partial discharge < 5 pC

Input to Output Test Voltage, Method a**,

V_PR

1968

8000

V_peak

V

_IORMx 1.6=V_PR, Type and Sample Test, t_m=10 sec, Partial discharge < 5 pC

Highest Allowable Overvoltage (Transient Overvoltage t_ini= 60 sec)

V_IOTM

Safety-limiting values – maximum values allowed in the event of a failure.

Case Temperature

T_S

175

ꢁC

Input Current

I_{S, INPUT}

P_{S, OUTPUT}

R_S

400

mA

mW

ꢂ

Output Power

1200

>10⁹

Insulation Resistance at T_S, V_IO= 500 V

*

Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

Surface mount classiﬁcation is class A in accordance with CECCOO802.

** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/

DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test proﬁles.

Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)

4

Table 2. Insulation and Safety Related Speciﬁcations

Parameter

Symbol

ACPL-332J Units

Conditions

Minimum External Air Gap

(Clearance)

L(101)

8.3

0.5

Mm

Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking

(Creepage)

L(102)

CTI

Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic Gap

(Internal Clearance)

Through insulation distance conductor to conductor,

usually the straight line distance thickness between

the emitter and detector.

Tracking Resistance

(Comparative Tracking Index)

>175

IIIa

V

DIN IEC 112/VDE 0303 Part 1

Isolation Group

Material Group (DIN VDE 0110, 1/89, Table 1)

Table 3. Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

125

105

Units

°C

Note

Storage Temperature

Operating Temperature

T_S

T_A

-55

-40

°C

2

Output IC Junction Temperature

Average Input Current

T_J

125

25

°C

mA

A

2

1

I_F(AVG)

I_F(TRAN)

Peak Transient Input Current,

(<1 μs pulse width, 300pps)

1.0

Reverse Input Voltage

V_R

5

V

“High”Peak Output Current

“Low”Peak Output Current

Positive Input Supply Voltage

FAULT Output Current

I_OH(PEAK)

I_OL(PEAK)

V_CC1

2.5

A

3

2.5

A

-0.5

5.5

V

I_FAULT

8.0

mA

V

FAULT Pin Voltage

V_FAULT

(V_CC2- V_EE)

(V_E- V_EE)

(V_CC2- V_E)

V_O(PEAK)

I_Clamp

-0.5

V_CC1

33

Total Output Supply Voltage

Negative Output Supply Voltage

Positive Output Supply Voltage

Gate Drive Output Voltage

Peak Clamping Sinking Current

Miller Clamping Pin Voltage

DESAT Voltage

V

15

V

6

33 - (V_E- V_EE)

V_CC2

1.7

V

A

V_Clamp

V_DESAT

P_O

-0.5

V_E

V_CC2

V_E+ 10

600

V

Output IC Power Dissipation

Input IC Power Dissipation

Solder Reﬂow Temperature Proﬁle

mW

2

P_I

150

See Package Outline Drawings section

Table 4. Recommended Operating Conditions

Parameter

Symbol

Min.

- 40

15

Max.

Units

°C

V

Note

Operating Temperature

Total Output Supply Voltage

Negative Output Supply Voltage

Positive Output Supply Voltage

Input Current (ON)

T_A

105

2

7

4

(V_CC2- V_EE)

(V_E- V_EE)

(V_CC2- V_E)

I_F(ON)

30

0

15

V

15

30 - (V_E- V_EE)

V

8

12

mA

V

Input Voltage (OFF)

V_F(OFF)

- 3.6

0.8

5

Table 5. Electrical Speciﬁcations (DC)

Unless otherwise noted, all typical values at T = 25°C, V

- V = 30 V, V - V = 0 V;

EE E EE

A

CC2

all Minimum/Maximum speciﬁcations are at Recommended Operating Conditions. Positive Supply Voltage used.

Parameter

FAULT Logic Low

Output Voltage

Symbol

V_FAULTL

Min.

Typ.

0.1

Max.

0.4

Units

V

Test Conditions

Fig.

Note

I_FAULT= 1.1 mA, V_CC1= 5.5V

I_FAULT= 1.1 mA, V_CC1= 3.3V

V_FAULT= 5.5 V, V_CC1= 5.5V

0.1

0.4

V

FAULT Logic High

Output Current

I_FAULTH

0.02

0.002

-1.5

0.5

μA

A

V_FAULT= 3.3 V, V_CC1= 3.3V

0.3

High Level

Output Current

I_OH

-0.5

-2.0

0.5

2.0

90

V_O= V_CC2- 4

2, 4,

21

5

3

5

3

6

A

V_O= V_CC2– 15

V_O= V_EE+ 2.5

V_O= V_EE+ 15

V_OUT- V_EE= 14 V

Low Level

Output Current

I_OL

1.5

A

3, 5,

22

A

Low Level Output Current

During Fault Condition

I_OLF

140

230

0.5

mA

High Level

Output Voltage

V_OH

V_CC-2.9 V_CC-2.0

V

I_O= -650 μA

I_O= 100 mA

4, 6,

23

7, 8, 9

23

Low Level

Output Voltage

V_OL

0.17

2.0

V

5, 7,

24

Clamp Pin

Threshold Voltage

V_tClamp

I_CL

V

Clamp Low Level

Sinking Current

0.35

1.1

2.5

-0.24

30

A

V_O= V_EE+ 2.5

I_O= 0 mA

8

High Level

Supply Current

I_CC2H

I_CC2L

I_CHG

I_DSCHG

5

mA

9, 10,

25,

26

9

Low Level

Supply Current

5

I_O= 0 mA

Blanking Capacitor

Charging Current

-0.13

10

-0.33

V_DESAT= 2 V

V_DESAT= 7.0 V

11, 27 9, 10

28

Blanking Capacitor

Discharge Current

DESAT Threshold

UVLO Threshold

V_DESAT

V_UVLO+

6

6.5

7.5

V

V_CC2-V_E>V_UVLO-

V_O> 5 V

12

9

10.5

11.6

12.5

7, 9,

11

V_UVLO-

9.2

0.4

10.3

1.3

11.1

8

V

V_O< 5 V

7, 9,

12

UVLO Hysteresis

(V_UVLO+

- V_UVLO-

V

)

Threshold Input Current

Low to High

I_FLH

2.0

mA

V

I_O= 0 mA, V_O> 5 V

Threshold Input Voltage

High to Low

V_FHL

0.8

1.2

Input Forward Voltage

V_F

1.6

1.95

V

I_F= 10 mA

Temperature Coeﬃcient

of Input Forward Voltage

ꢃV_F/ꢃT_A

-1.3

mV/°C

Input Reverse

Breakdown Voltage

BV_R

C_IN

5

V

I_R= 10 ꢄA

Input Capacitance

70

pF

f = 1 MHz, V_F= 0 V

6

Table 6. Switching Speciﬁcations (AC)

Unless otherwise noted, all typical values at T = 25°C, V

- V = 30 V, V - V = 0 V;

EE E EE

A

CC2

all Minimum/Maximum speciﬁcations are at Recommended Operating Conditions. Only Positive Supply Voltage used.

Parameter

Symbol

Min. Typ.

Max. Units

Test Conditions

Fig.

Note

Propagation Delay Time

to High Output Level

t_PLH

100

180

250

ns

R_g= 10 ꢂ,

1, 13,

14, 15,

16, 29

13, 15

C_g= 10 nF,

f = 10 kHz,

Duty Cycle = 50%,

I_F= 10 mA,

Propagation Delay Time

to Low Output Level

t_PHL

100

180

250

ns

1, 13,

14, 15,

16, 29

V

_CC2= 30 V

Pulse Width Distortion

PWD

-100 20

-350

100

350

ns

14, 17

17, 16

Propagation Delay

(t_PHL- t_PLH

)

Diﬀerence Between

Any Two Parts or Channels

PDD

Rise Time

Fall Time

t_R

t_F

50

ns

μs

DESAT Sense to

90%VO Delay

t_DESAT(90%)

0.15

0.5

3

C_DESAT= 100pF, R_g= 10 ꢂ,

C_g= 10 nF, V_CC2= 30 V

17, 30, 19

37

DESAT Sense to

10% VO Delay

t_DESAT(10%)

2

μs

C_DESAT= 100pF, R_g= 10 ꢂ,

C_g= 10 nF, V_CC2= 30 V

18, 19,

20, 30,

37

DESAT Sense to Low Level

FAULT Signal Delay

t_DESAT(FAULT)

t_DESAT(LOW)

t_DESAT(MUTE)

0.25

0.5

C_DESAT= 100pF, R_F= 2.1 kꢂ,

R_g= 10 ꢂ, C_g= 10 nF,

V_CC2= 30 V

30, 37 18

DESAT Sense to DESAT

Low Propagation Delay

C_DESAT= 100pF, R_F= 2.1 kꢂ,

R_g= 10 ꢂ, C_g= 10 nF,

V_CC2= 30 V

30, 37 19

DESAT Input Mute

5

μs

37

20

RESET to High Level

FAULT Signal Delay

t_RESET(FAULT)0.3

1

2.0

2.5

C_DESAT= 100pF, RF = 2.1 kꢂ,

Rg = 10 ꢂ, Cg = 10 nF,

V_CC1= 5.5V, V_CC2= 30 V

0.8

1.5

μs

C_DESAT= 100pF, R_F= 2.1 kꢂ,

Rg = 10 ꢂ, Cg = 10 nF,

V_CC1= 3.3V, V_CC2= 30 V

Output High Level Common

Mode Transient Immunity

|CM_H|

|CM_L|

15

25

kV/μs

T_A= 25°C, I_F= 10 mA

V_CM= 1500 V, V_CC2= 30 V

31, 32, 21

33, 34

Output Low Level Common

Mode Transient Immunity

T_A= 25°C, V_F= 0 V

V_CM= 1500 V, V_CC2= 30 V

31, 32, 22

33, 34

7

Table 7. Package Characteristics

Parameter

Symbol

Min.

Typ.

Max. Units

Test Conditions

Fig.

Note

Input-Output Momentary

Withstand Voltage

V_ISO

5000

V_rms

RH < 50%, t = 1 min.,

T_A= 25°C

24, 25

Input-Output Resistance

Input-Output Capacitance

R_I-O

> 10⁹

1.3

ꢂ

V

_I-O= 500 V

25

C_I-O

pF

freq=1 MHz

T_A= 25°C

Output IC-to-Pins 9 &10

Thermal Resistance

ꢅ_09-10

30

°C/W

Notes:

1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.

2. In order to achieve the absolute maximum power dissipation speciﬁed, pins 4, 9, and 10 require ground plane connections and may require

airﬂow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature

and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation

achievable will depend on the application environment (PCB Layout, air ﬂow, part placement, etc.). See the Recommended PCB Layout section

in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power

dissipation does not require derating.

3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with I peak minimum = 2.0 A. Derate

O

linearly from 3.0 A at +25°C to 2.5 A at +105°C. This compensates for increased I

due to changes in V over temperature.

OPEAK

OL

4. This supply is optional. Required only when negative gate drive is implemented.

5. Maximum pulse width = 50 μs.

6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.

7. 15 V is the recommended minimum operating positive supply voltage (V - V ) to ensure adequate margin in excess of the maximum V

UVLO+

CC2

E

threshold of 12.5V. For High Level Output Voltage testing, V is measured with a dc load current. When driving capacitive loads, V will

OH

approach V as I approaches zero units.

CC

OH

8. Maximum pulse width = 1.0 ms.

9. Once V of the ACPL-332J is allowed to go high (V

- V > V

E

), the DESAT detection feature of the ACPL-332J will be the primary source of

O

CC2

UVLO+

IGBT protection. UVLO is needed to ensure DESAT is functional. Once V

is increased from 0V to above V , DESAT will remain functional

UVLO+

CC2

until V

is decreased below V

. Thus, the DESAT detection and UVLO features of the ACPL-332J work in conjunction to ensure constant

UVLO-

CC2

IGBT protection.

10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.

11. This is the “increasing”(i.e. turn-on or “positive going”direction) of V - V

CC2

E

12. This is the “decreasing”(i.e. turn-oﬀ or “negative going”direction) of V

- V

CC2

E

13. This load condition approximates the gate load of a 1200 V/150A IGBT.

14. Pulse Width Distortion (PWD) is deﬁned as |t - t | for any given unit.

PHL PLH

15. As measured from I to V .

F

O

16. The diﬀerence between t

and t

between any two ACPL-332J parts under the same test conditions.

PLH

PHL

17. As measured from ANODE, CATHODE of LED to V

OUT

18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.

19. This is the amount of time the DESAT threshold must be exceeded before V

voltage dependent.

begins to go low, and the FAULT output to go low. This is supply

OUT

20. Auto Reset: This is the amount of time when V

will be asserted low after DESAT threshold is exceeded. See the Description of Operation (Auto

OUT

Reset) topic in the application information section.

21. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the

CM

output will remain in the high state (i.e., V > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode.

O

22. Common mode transient immunity in the low state is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the

CM

output will remain in a low state (i.e., V < 1.0 V or FAULT < 0.8 V).

O

23. To clamp the output voltage at V - 3 V , a pull-down resistor between the output and V is recommended to sink a static current of 650 μA

CC

BE

EE

while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down

resistor is not used.

24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is

performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table.

25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.

8

I

F

t

f

r

90%

50%

10%

V

OUT

t

PHL

PLH

Figure 1. VOUT propagation delay waveforms

3.0

2.5

2.0

1.5

1.0

5

4

3

2

1

0

-----V

___V

=V_EE+15V

=V_EE+2.5V

OUT

-40

-20

0

20

40

60

80

105

-40

-20

0

20

40

60

80

105

T _A- TEMPERATURE - ^oC

T_A- TEMPERATURE - ^oC

Figure 2. I_OHvs. temperature

0

Figure 3. I_OLvs. temperature

0.25

0.2

0.15

0.1

0.05

0

____

= -650uA

I _OUT

-0.5

-1

-1.5

-2

-2.5

-40

-20

0

20

40

60

80

105

-40

-20

0

20

40

60

80

105

T_A- TEMPERATURE - ^o

C

T_A- TEMPERATURE - ^oC

Figure 4. V_OHvs. temperature

Figure 5. V_OLvs. temperature

9

8

7

6

5

4

3

2

1

0

30

29

28

27

26

25

_ _ _ _ 105 ^oC

______ 25 ^oC

--------- -40 ^oC

o

_ _ _ _ 105

C

______ 25 ^oC

o

--------- -40

C

0

0.5

1

1.5

2

2.5

0.0

0.2

0.4

0.6

0.8

1.0

I_OH- OUTPUT HIGH CURRENT - A

I

_oL- OUTPUT LOW CURRENT - A

Figure 6. V_OHvs. I_OH

Figure 7. V_OLvs. I_OL

3.50

3.25

3.00

2.75

2.50

2.25

2.00

4

3

2

1

0

- ---- ----I

CC2

H

I_CC2

________

L

-40

-20

0

20

40

60

80

105

-40

-20

0

20

40

60

80

105

T_A- TEMPERATURE - ^oC

T _A-TEMPERATURE-

^oC

Figure 8. I_CLvs. temperature

2.65

Figure 9. I_CC2vs. temperature

-0.20

---------I

Cc 2

H

I_CC

________

_

2

L

2.55

2.45

-0.25

-0.30

-0.35

2.35

2.25

15

20

25

30

-40

-20

0

20

40

60

^oC

80

105

V

_CC2- OUTPUR SUPPLY VOLTAGE - V

T _A- TEMPERATURE -

Figure 11. I_CHGvs. temperature

Figure 10. I_CC2vs. V_CC2

10

7.5

7.0

6.5

6.0

300

250

200

150

100

---------- t_PLH

_______t _PHL

-40

-20

0

20

40

60

^oC

80

105

-40

-20

0

20

40

60

^oC

80

105

T _A- TEMPERATURE -

Figure 13. Propagation delay vs. temperature

Figure 12. DESAT threshold vs. temperature

300

250

200

150

100

---------- t_PLH

_______t_PHL

250

200

150

100

0

10

20

30

40

50

15

20

25

30

LOAD RESISTANCE - ohm

Vcc - SUPPLY VOLTAGE - V

Figure 14. Propagation delay vs. supply voltage

Figure 15. Propagation delay vs. load resistance

300

---------- t

PLH

_______t_PHL

200

100

0

10

20

30

40

50

LOAD CAPACITANCE - nF

Figure 16. Propagation delay vs. load capacitance

11

3.0

2.5

2.0

1.5

1.0

300

250

200

150

100

------- V_cc2=15V

_____V =30V

cc2

-40

-20

0

20

40

60

80

105

-40

-20

0

20

40

60

80

105

T _A- TEMPERATURE - ^oC

T

- TEMPERATURE - ^oC

A

Figure 17. DESAT sense to 90% VOUT delay vs. temperature

Figure 18. DESAT sense to 10% VOUT delay vs. temperature

4.0

0.012

------- V_cc2=15V

------- V =15V

_____V_cc2=30V

cc2

_____V_cc2=30V

3.0

0.008

0.004

0.000

2.0

1.0

0.0

0

10

20

30

40

50

10

20

30

40

50

LOAD CAPACITANCE - nF

LOAD RESISTANCE - ohm

Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance

Figure 19. DESAT sense to 10% VOUT delay vs. load resistance

12

FAULT

0.1μF

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

V_CC1

DESAT 14

V_CC213

V_S

15V Pulsed

+

CATHODE

ANODE

CATHODE

V_EE12

_

I_OUT

V_OUT11

V_CLAMP10

30V

+

_

10mA

V_EE

9

Figure 21. I_OHPulsed test circuit

1

2

3

4

5

6

7

8

V_S

V_E16

V_CC1

V_LED15

DESAT 14

V_CC213

FAULT

V_S

0.1μF

15V Pulsed

CATHODE

ANODE

V_EE12

I_OUT

V_OUT11

30V

0.1μF

+

_

V_CLAMP10

+

_

CATHODE

V_EE

9

Figure 22. I_OLPulsed test circuit

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢊ_ꢎ

ꢊ_ꢋꢀꢅ

ꢊ_ꢑꢑꢀ

ꢊ_ꢌꢋꢍꢀꢄ

ꢖꢏꢓꢌꢐ

ꢊ_ꢎ

ꢍꢋꢎꢏꢐ ꢀꢃ

ꢊ_ꢑꢑꢁꢀꢂ

ꢊ_ꢋꢋꢀꢁ

ꢈꢛꢀꢜꢖ

ꢑꢏꢐꢗꢒꢍꢋ

ꢏꢘꢒꢍꢋ

ꢑꢏꢐꢗꢒꢍꢋ

ꢊ_ꢒꢓꢐ

ꢊ_ꢒꢓꢐꢀꢀ

ꢊ_{ꢑꢌꢏꢔꢕ}ꢀꢈ

ꢙ ^ꢂꢈꢊ

ꢈꢛꢀꢜꢖ

ꢚ

ꢅꢄꢈꢜꢏꢝ

ꢀꢈ!ꢏ

ꢊ_ꢋꢋ

ꢉ

Figure 23. V_OHPulsed test circuit

13

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

V_CC1

FAULT

V_S

DESAT 14

V_CC213

0.1μF

100mA

CATHODE

ANODE

CATHODE

V_EE12

V_OUT

V_OUT11

V_CLAMP10

30V

0.1μF

+

_

V_EE

9

Figure 24. V_OLPulsed test circuit

1

2

3

4

5

6

7

8

V_S

V_E16

V_CC1

V_LED15

DESAT 14

V_CC213

FAULT

V_S

0.1μF

I_CC2

CATHODE

ANODE

CATHODE

V_EE12

V_OUT11

30V

0.1μF

+

_

V_CLAMP10

10mA

V_EE

9

Figure 25. I_CC2Htest circuit

1

2

3

4

5

6

7

8

V_S

V_E16

V_CC1

V_LED15

FAULT

V_S

DESAT 14

V_CC213

V_EE12

0.1μF

I _CC2

CATHODE

ANODE

CATHODE

V_OUT11

V_CLAMP10

30V

0.1μF

+

_

V_EE

9

Figure 26. I_CC2Ltest circuit

14

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

I_CHG

V_CC1

FAULT

V_S

DESAT 14

V_CC213

0.1μF

CATHODE

ANODE

CATHODE

V_EE12

V_OUT11

V_CLAMP10

30V

0.1μF

+

_

10mA

V_EE

9

Figure 27. I_CHGPulsed test circuit

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

_

+

7V

V_CC1

FAULT

V_S

DESAT 14

V_CC213

0.1μF

IDSCHG

CATHODE

ANODE

CATHODE

V_EE12

V_OUT11

V_CLAMP10

30V

0.1μF

+

_

V_EE

9

Figure 28. I_DSCHGtest circuit

1

2

3

4

5

6

7

8

V_S

V_E16

V_CC1

V_LED15

DESAT 14

V_CC213

FAULT

V_S

0.1μF

CATHODE

ANODE

CATHODE

V_EE12

V_OUT

V_OUT11

30V

0.1μF

10Ω

10nF

+

_

V_CLAMP10

V_EE

9

10mA, 10kHz,

50% Duty Cycle

Figure 29. t_PLH, t_PHL, t_f, t_r, test circuit

15

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

V_IN

V_CC1

2.1kΩ

V_FAULT

FAULT

V_S

DESAT 14

V_CC213

0.1μF

+

5V

_

CATHODE

ANODE

CATHODE

V_EE12

V_OUT

V_OUT11

V_CLAMP10

30V

0.1μF

10Ω

+

_

10mA

10nF

V_EE

9

Figure 30. t_DESATfault test circuit

1

V_S

V_E16

5V

2

V_CC1

V_LED15

2.1kΩ

3

FAULT

V_S

DESAT 14

V_CC213

V_EE12

15pF

30V

4

SCOPE

0.1μF

5

6

CATHODE

ANODE

CATHODE

10Ω

V_OUT11

V_CLAMP10

0.1μF

430Ω

7

10nF

8

V_EE

9

V_CM

Figure 31. CMR Test circuit LED2 oﬀ

1

V_S

V_E16

V_LED15

5V

2

V_CC1

2.1kΩ

3

FAULT

V_S

DESAT 14

V_CC213

15pF

30V

4

SCOPE

0.1μF

5

6

CATHODE

ANODE

CATHODE

V_EE12

10Ω

V_OUT11

V_CLAMP10

0.1μF

430Ω

7

10nF

8

V_EE

9

V_CM

Figure 32. CMR Test Circuit LED2 on

16

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

5V

V_CC1

2.1kΩ

DESAT 14

V_CC213

FAULT

15pF

30V

V_S

0.1μF

CATHODE

ANODE

CATHODE

V_EE12

SCOPE

10Ω

V_OUT11

V_CLAMP10

0.1μF

430Ω

10nF

V_EE

9

V_CM

Figure 33. CMR Test circuit LED1 oﬀ

1

V_S

V_E16

5V

2

V_CC1

V_LED15

DESAT 14

V_CC213

2.1kΩ

3

FAULT

V_S

15pF

30V

4

0.1μF

5

CATHODE

ANODE

CATHODE

V_EE12

SCOPE

10Ω

6

V_OUT11

0.1μF

Ω

430

7

8

V_CLAMP10

10nF

V_EE

9

V_CM

Figure 34. CMR Test Circuit LED1 on

17

Application Information

Product Overview Description

13

The ACPL-332J is a highly integrated power control

device that incorporates all the necessary components

for a complete, isolated IGBT / MOSFET gate drive circuit

with fault protection and feedback into one SO-16

package. Active Miller clamp function eliminates the

need of negative gate drive in most application and

allows the use of simple bootstrap supply for high side

driver. An optically isolated power output stage drives

IGBTs with power ratings of up to 150 A and 1200 V. A

high speed internal optical link minimizes the propaga-

tion delays between the microcontroller and the IGBT

while allowing the two systems to operate at very large

common mode voltage diﬀerences that are common

in industrial motor drives and other power switching

applications. An output IC provides local protection

for the IGBT to prevent damage during over current,

and a second optical link provides a fully isolated fault

status feedback signal for the microcontroller. A built

in “watchdog” circuit, UVLO monitors the power stage

supply voltage to prevent IGBT caused by insuﬃcient

gate drive voltages. This integrated IGBT gate driver is

designed to increase the performance and reliability of

a motor drive without the cost, size, and complexity of a

discrete design.

V_CC2

UVLO

6, 7

5, 8

D

R

I

V

E

R

ANODE

11

V_OUT

DESAT

CATHODE

LED1

14

DESAT

9, 12

V_EE

SHIELD

LED2

V_CLAMP

2

3

10

16

V_CC1

V_CLAMP

V_E

FAULT

1, 4

15

V_S

V_LED

SHIELD

Figure 35. Block Diagram of ACPL-332J

Recommended Application Circuit

The ACPL-332J has an LED input gate control, and an

open collector fault output suitable for wired ‘OR’ ap-

plications. The recommended application circuit shown

in Figure 36 illustrates a typical gate drive implementa-

tion using the ACPL-332J. The following describes about

driving IGBT. However, it is also applicable to MOSFET.

Depending upon the MOSFET or IGBT gate threshold

requirements, designers may want to adjust the VCC

Two light emitting diodes and two integrated circuits

housed in the same SO-16 package provide the input

control circuitry, the output power stage, and two optical

channels. The output Detector IC is designed manufac-

tured on a high voltage BiCMOS/Power DMOS process.

The forward optical signal path, as indicated by LED1,

transmits the gate control signal. The return optical signal

path, as indicated by LED2, transmits the fault status

feedback signal.

supply voltage (Recommended V = 17.5V for IGBT and

CC

12.5V for MOSFET).

The two supply bypass capacitors (0.1 μF) provide the

large transient currents necessary during a switching

transition. Because of the transient nature of the charging

currents, a low current (5mA) power supply suﬃces. The

Under normal operation, the LED1 directly controls the

IGBT gate through the isolated output detector IC, and

LED2 remains oﬀ. When an IGBT fault is detected, the

output detector IC immediately begins a “soft” shutdown

sequence, reducing the IGBT current to zero in a con-

trolled manner to avoid potential IGBT damage from

inductive over voltages. Simultaneously, this fault status

is transmitted back to the input via LED2, where the fault

latch disables the gate control input and the active low

fault output alerts the microcontroller.

desaturation diode D

DESAT

t

below 75ns (e.g. ERA34-10) and capacitor C

rr

necessary external components for the fault detection

circuitry. The gate resistor R serves to limit gate charge

current and controls the IGBT collector voltage rise

and fall times. The open collector fault output has a

passive pull-up resistor R (2.1 kꢂ) and a 330 pF ﬁltering

F

capacitor, C . A 47 kꢂ pull down resistor R

F

V

OUT

provides a predictable high level output voltage

(V ). In this application, the IGBT gate driver will shut

OH

down when a fault is detected and fault reset by next

cycle of IGBT turn on. Application notes are mentioned at

the end of this datasheet.

During power-up, the Under Voltage Lockout (UVLO)

feature prevents the application of insuﬃcient gate

voltage to the IGBT, by forcing the ACPL-332J’s output

low. Once the output is in the high state, the DESAT (VCE)

detection feature of the ACPL-332J provides IGBT pro-

tection. Thus, UVLO and DESAT work in conjunction to

provide constant IGBT protection.

18

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢍ_ꢑ

ꢍ_ꢎꢃꢈ

ꢍ_ꢏꢎꢐꢃꢇ

ꢋ'ꢃꢟꢙ

ꢍ_ꢔꢔꢃ

ꢔ_!ꢏꢒꢛ"

ꢃꢋꢋꢞΩ

ꢜ_ꢙ

ꢔ_ꢙ

ꢐ_{ꢐꢎꢑꢒꢓ}

ꢋ'ꢃꢟꢙ

ꢁ

ꢙꢒꢖꢏꢓ

ꢍ_ꢑ

ꢐꢎꢑꢒꢓ ꢃꢆ

ꢍ_ꢔꢔꢄꢃꢅ

ꢂ

ꢔꢒꢓꢚꢕꢐꢎ

ꢒꢛꢕꢐꢎ

ꢔꢒꢓꢚꢕꢐꢎ

ꢍ_ꢎꢎꢃꢄ

ꢁꢞꢚꢍꢐꢔ

ꢁ

ꢂ

ꢜ_ꢝ

ꢁ

ꢍ_ꢔꢎ

$

ꢍ_ꢕꢖꢓꢃꢃ

ꢍ_{ꢔꢏꢒꢗꢘ}ꢃꢋ

#ꢃ

#ꢄ

ꢜ

ꢅ$ꢘꢚꢒꢑꢎ

ꢒꢔ

ꢜ_{ꢘꢖꢏꢏ$ꢐꢕ&ꢛ}

ꢁ

ꢂ

ꢁ

ꢍ_ꢔꢎ

$

ꢍ_ꢎꢎ

ꢌ

$ ꢚꢍꢐꢔ

Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp

Description of Operation

Normal Operation

During normal operation, V

of the ACPL-332J is con-

activated is an internal feedback channel which brings

the FAULT output low for the purpose of notifying the

micro-controller of the fault condition.

OUT

trolled by input LED current IF (pins 5, 6, 7 and 8), with

the IGBT collector-to-emitter voltage being monitored

through DDESAT. The FAULT output is high. See Figure 37.

Fault Reset

Fault Condition

Once fault is detected, the output will be muted for 5 μs

(minimum). All input LED signals will be ignored during

the mute period to allow the driver to completely soft

shut-down the IGBT. The fault mechanism can be reset by

the next LED turn-on after the 5us (minimum) mute time.

See Figure 37.

The DESAT pin monitors the IGBT V voltage. When the

voltage on the DESAT pin exceeds 6.5 V while the IGBT is

ce

on, V

is slowly brought low in order to “softly” turn-oﬀ

OUT

the IGBT and prevent large di/dt induced voltages. Also

:

ꢐꢎꢑꢒꢓ;ꢏꢕ&<

ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢁꢄ

ꢅꢈꢉꢊꢇꢋꢄꢃꢌꢁꢄ

ꢇꢁꢍꢃꢄꢎꢏꢐꢄ

ꢃꢈꢉꢇꢑꢆꢇ

+

ꢙ

ꢈ'ꢇꢍ

ꢇꢋ/

ꢍ_{ꢐꢎꢑꢒꢓ}

:

!ꢏꢒꢛ"

ꢐꢎꢑꢒꢓ;ꢃꢋ/<

ꢌꢋ/

ꢍ_ꢕꢖꢓ

ꢃꢋ/

:

ꢜꢎꢑꢎꢓ;ꢙꢒꢖꢏꢓ<

:

ꢐꢎꢑꢒꢓ;ꢌꢋ/<

ꢇꢋ/

ꢙꢒꢖꢏꢓ

:

ꢐꢎꢑꢒꢓ;ꢙꢒꢖꢏꢓ<

:

ꢐꢎꢑꢒꢓ;ꢗꢖꢓꢎ<<

Figure 37. Fault Timing diagram

19

Output Control

Slow IGBT Gate Discharge during Fault Condition

The outputs (V

trolled by the combination of I , UVLO and a detected

IGBT Desat condition. Once UVLO is not active (V

and FAULT) of the ACPL-332J are con-

When a desaturation fault is detected, a weak pull-down

device in the ACPL-332J output drive stage will turn on

to ‘softly’ turn oﬀ the IGBT. This device slowly discharges

the IGBT gate to prevent fast changes in drain current

that could cause damaging voltage spikes due to lead

and wire inductance. During the slow turn oﬀ, the large

output pull-down device remains oﬀ until the output

OUT

F

-

CC2

V > V

), VOUT is allowed to go high, and the DESAT

UVLO

E

(pin 14) detection feature of the ACPL-332J will be the

primary source of IGBT protection. Once V is increased

from 0V to above V

CC2

, DESAT will remain functional

UVLO+

until V

is decreased below V

.

Thus, the DESAT

voltage falls below V + 2 Volts, at which time the large

pull down device clamps the IGBT gate to V .

EE

CC2

UVLO-

EE

detection and UVLO features of the ACPL-332J work in

conjunction to ensure constant IGBT protection.

DESAT Fault Detection Blanking Time

Desaturation Detection and High Current Protection

The DESAT fault detection circuitry must remain disabled

for a short time period following the turn-on of the IGBT

to allow the collector voltage to fall below the DESAT

threshold. This time period, called the DESAT blanking

time is controlled by the internal DESAT charge current,

the DESAT voltage threshold, and the external DESAT

capacitor.

The ACPL-332J satisﬁes these criteria by combining a

high speed, high output current driver, high voltage

optical isolation between the input and output, local

IGBT desaturation detection and shut down, and an

optically isolated fault status feedback signal into a single

16-pin surface mount package.

The fault detection method, which is adopted in the

ACPL-332J, is to monitor the saturation (collector)

voltage of the IGBT and to trigger a local fault shutdown

sequence if the collector voltage exceeds a predeter-

mined threshold. A small gate discharge device slowly

reduces the high short circuit IGBT current to prevent

damaging voltage spikes. Before the dissipated energy

can reach destructive levels, the IGBT is shut oﬀ. During

the oﬀ state of the IGBT, the fault detect circuitry is simply

disabled to prevent false ‘fault’signals.

The nominal blanking time is calculated in terms of

external capacitance (C

), FAULT threshold voltage

BLANK

(V

DESAT

), and DESAT charge current (I

) as t

=

CHG

BLANK

C

BLANK

x V

/ I

CHG

. The nominal blanking time with

DESAT

the recommended 100pF capacitor is 100pF * 6.5 V / 240

μA = 2.7 μsec.

The capacitance value can be scaled slightly to adjust the

blanking time, though a value smaller than 100 pF is not

recommended. This nominal blanking time represents

the longest time it will take for the ACPL-332J to respond

to a DESAT fault condition. If the IGBT is turned on while

the collector and emitter are shorted to the supply rails

(switching into a short), the soft shut-down sequence

will begin after approximately 3 μsec. If the IGBT collector

and emitter are shorted to the supply rails after the IGBT

is already on, the response time will be much quicker due

to the parasitic parallel capacitance of the DESAT diode.

The recommended 100pF capacitor should provide

adequate blanking as well as fault response times for

most applications.

The alternative protection scheme of measuring IGBT

current to prevent desaturation is eﬀective if the short

circuit capability of the power device is known, but

this method will fail if the gate drive voltage decreases

enough to only partially turn on the IGBT. By directly

measuring the collector voltage, the ACPL-332J limits the

power dissipation in the IGBT even with insuﬃcient gate

drive voltage. Another more subtle advantage of the de-

saturation detection method is that power dissipation in

the IGBT is monitored, while the current sense method

relies on a preset current threshold to predict the safe

limit of operation. Therefore, an overly conservative over

current threshold is not needed to protect the IGBT.

I

UVLO(V -V )

DESAT Function

Not Active

Pin 3 (FAULT) Output

High

V

OUT

F

CC2

E

ON

OFF

Active

Low

High

Low

Not Active

Active

Active (with DESAT fault)

Active (no DESAT fault)

Not Active

Low (FAULT)

High (or no fault)

High

Not Active

High

20

Under Voltage Lockout

ꢀ ₁

V_S

V_E16

V_LED15

The ACPL-332J Under Voltage Lockout (UVLO) feature is

designed to prevent the application of insuﬃcient gate

voltage to the IGBT by forcing the ACPL-332J output

low during power-up. IGBTs typically require gate

voltages of 15 V to achieve their rated V

At gate voltages below 13 V typically, the V

increases dramatically, especially at higher currents.

At very low gate voltages (below 10 V), the IGBT may

operate in the linear region and quickly overheat.

The UVLO function causes the output to be clamped

2

3

4

5

6

7

8

V_CC1

FAULT

V_S

DESAT 14

V_CC213

V_CC

voltage.

voltage

CE(ON)

CATHODE

ANODE

CATHODE

V_EE12

R_G

V_OUT11

V_CLAMP10

R_PULL-DOWN

whenever insuﬃcient operating supply (V ) is applied.

CC2

Once V

exceeds V

(the positive-going UVLO

CC2

UVLO+

V_EE

9

threshold), the UVLO clamp is released to allow the

device output to turn on in response to input signals. As

V

is increased from 0 V (at some level below V

),

CC2

UVLO+

Figure 38. Output pull-down resistor.

ﬁrst the DESAT protection circuitry becomes active. As

is further increased (above V ), the UVLO clamp

V

CC2

UVLO+

DESAT Pin Protection Resistor

is released. Before the time the UVLO clamp is released,

the DESAT protection is already active. Therefore, the

UVLO and DESAT Fault detection feature work together

to provide seamless protection regardless of supply

The freewheeling of ﬂyback diodes connected across

the IGBTs can have large instantaneous forward voltage

transients which greatly exceed the nominal forward

voltage of the diode. This may result in a large negative

voltage spike on the DESAT pin which will draw substan-

tial current out of the driver if protection is not used. To

limit this current to levels that will not damage the driver

IC, a 100 ohm resistor should be inserted in series with

the DESAT diode. The added resistance will not alter the

DESAT threshold or the DESAT blanking time.

voltage (V ).

CC2

Active Miller Clamp

A Miller clamp allows the control of the Miller current

during a high dV/dt situation and can eliminate the use

of a negative supply voltage in most of the applications.

During turn-oﬀ, the gate voltage is monitored and the

clamp output is activated when gate voltage goes below

2V (relative to V ). The clamp voltage is V +2.5V typ

ꢀ ₁

V_S

V_E

16

EE

OL

for a Miller current up to 1100mA. The clamp is disabled

when the LED input is triggered again.

100pF

100 Ω

2

3

4

5

6

7

8

V_CC1

V_LED15

DESAT 14

V_CC213

D_DESAT

FAULT

V_S

Other Recommended Components

V_CC

The application circuit in Figure 36 includes an output

pull-down resistor, a DESAT pin protection resistor, a

FAULT pin capacitor, and a FAULT pin pullup resistor and

Active Miller Clamp connection.

CATHODE

ANODE

CATHODE

V_EE12

R_G

V_OUT11

Output Pull-Down Resistor

V_CLAMP10

During the output high transition, the output voltage

V_EE

9

rapidly rises to within 3 diode drops of V . If the output

CC2

current then drops to zero due to a capacitive load, the

output voltage will slowly rise from roughly V -3(V

)

CC2

BE

to V

within a period of several microseconds. To limit

CC2

Figure 39. DESAT pin protection.

the output voltage to V -3(V ), a pull-down resistor,

CC2

BE

Capacitor on FAULT Pin for High CMR

R

between the output and V is recommend-

PULL-DOWN

EE

ed to sink a static current of several 650 μA while the

output is high. Pull-down resistor values are dependent

on the amount of positive supply and can be adjusted

Rapid common mode transients can aﬀect the fault pin

voltage while the fault output is in the high state. A 330

pF capacitor should be connected between the fault pin

and ground to achieve adequate CMOS noise margins at

the speciﬁed CMR value of 15 kV/μs. The added capaci-

tance does not increase the fault output delay when a

desaturation condition is detected.

according to the formula, R

650 μA.

= [V -3 * (V )] /

pull-down

CC2 BE

21

Pull-up Resistor on FAULT Pin

The FAULT pin is an open collector output and therefore

requires a pull-up resistor to provide a high-level signal.

Also the FAULT output can be wire ‘OR’ed together with

other types of protection (e.g. over-temperature, over-

voltage, over-current ) to alert the microcontroller.

Other Possible Application Circuit (Output Stage)

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

DESAT 14

V_CC213

0.1μF 0.1μF

V_CC1

FAULT

V_S

Optional R₂

0.1μF

Optional R₁

CATHODE

ANODE

CATHODE

V_EE12

ꢠ HVDC

ꢠ

_

R_G

ꢠ

V_CE

-

V_OUT11

Q1

Q2

3-PHASE

AC

10

V_CLAMP

*

ꢠ

_

R_PULL-DOWN

ꢠ

V_CE

-

V_EE

9

- HVDC

Figure 40. IGBT drive with negative gate drive, external booster and desaturation detection (V_CLAMPshould be connected to V_EEwhen it is not used)

VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology

1

2

3

4

5

6

7

8

V_S

V_E16

V_LED15

DESAT 14

V_CC213

0.1μF 0.1μF

V_CC1

FAULT

V_S

Optional R₂

0.1μF

Optional R₁

CATHODE

ANODE

CATHODE

V_EE12

ꢠ HVDC

ꢠ

_

R_G

ꢠ

V_CE

-

V_OUT11

Q1

Q2

3-PHASE

AC

10

V_CLAMP

*

R_PULL-DOWN

ꢠ

V_CE

-

V_EE

9

- HVDC

R₃

Figure 41. Large IGBT drive with negative gate drive, external booster. V_CLAMPcontrol secondary discharge path for higher power application.

22

Thermal Model

where P = power into input IC and P = power into

The ACPL-332J is designed to dissipate the majority of

the heat through pins 1, 4, 5 & 8 for the input IC and pins

i

o

output IC. Since θ and θ

are dependent on PCB

5A

9,12A

layout and airﬂow, their exact number may not be

available. Therefore, a more accurate method of calcu-

lating the junction temperature is with the following

equations:

9 & 12 for the output IC. (There are two V pins on the

EE

output side, pins 9 and 12, for this purpose.) Heat ﬂow

through other pins or through the package directly into

ambient are considered negligible and not modeled

here.

T = P θ + T

ji

i

i5

P5

In order to achieve the power dissipation speciﬁed in

the absolute maximum speciﬁcation, it is imperative

that pins 5, 9, and 12 have ground planes connected to

them. As long as the maximum power speciﬁcation is

not exceeded, the only other limitation to the amount

of power one can dissipate is the absolute maximum

junction temperature speciﬁcation of 125°C. The junction

temperatures can be calculated with the following

equations:

T

= P θ

+ T

jo

o

o9,12 P9,12

These equations, however, require that the pin 5 and pins

9, 12 temperatures be measured with a thermal couple

on the pin at the ACPL-332J package edge.

If the calculated junction temperatures for the thermal

model in Figure 42 is higher than 125°C, the pin tem-

perature for pins 9 and 12 should be measured (at the

package edge) under worst case operating environment

for a more accurate estimate of the junction tempera-

tures.

T = P (θ + θ ) + T

ji

i

i5

5A

A

T

jo

= Po (θ

+ θ

) + T

9,12A A

o9,12

Tji = junction temperature of input side IC

Tjo = junction temperature of output side IC

TP5 = pin 5 temperature at package edge

TP9,12 = pin 9 and 12 temperature at package edge

θI5 = input side IC to pin 5 thermal resistance

θo9,12 = output side IC to pin 9 and 12 thermal resistance

θ5A = pin 5 to ambient thermal resistance

θ9,12A = pin 9 and 12 to ambient thermal resistance

*The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air ﬂow.

This value may increase or decrease by a factor of 2 depending on PCB layout and/or airﬂow.

Figure 42. ACPL-332J Thermal Model

Related Application Notes

AN5314 – Active Miller Clamp

AN5324 - Desaturation Fault Detection

AN5315 – “Soft”Turn-oﬀ Feature

AN1043 – Common-Mode Noise : Sources and Solutions

AN02-0310EN - Plastics Optocoupler Product ESD and Moisture Sensitivity

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.

AV02-0120EN - March 24, 2011

型号:	ACPL-332J
生命周期：	Active
IHS 制造商：	BROADCOM INC
包装说明：	SOP-16
Reach Compliance Code：	compliant
HTS代码：	8541.40.80.00
风险等级：	5.8
其他特性：	UL RECOGNIZED
配置：	SINGLE
最大正向电流：	0.025 A
标称滞后比：	1.3
最大绝缘电压：	3750 V
元件数量：	1
最大通态电流：	2.5 A
最高工作温度：	105 °C
最低工作温度：	-40 °C
光电设备类型：	LOGIC IC OUTPUT OPTOCOUPLER
最小供电电压：	15 V

电子百科

产品导航

产品型号ACPL-332J的概述

产品型号ACPL-332J的Datasheet PDF文件预览

ACPL-332J相关产品..

ACPL-332J相关文章

IC37:专业IC行业平台