AD8315ARMZ原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

50 dB GSM PA Controller

AD8315

Its high sensitivity allows control at low signal levels, thus

reducing the amount of power that needs to be coupled to

the detector.

FEATURES

Complete RF detector/controller function

>50 dB range at 0.9 GHz (−49 dBm to +2 dBm, re 50 Ω)

Accurate scaling from 0.1 GHz to 2.5 GHz

Temperature-stable linear-in-dB response

Log slope of 23 mV/dB, intercept at −60 dBm at 0.9 GHz

True integration function in control loop

Low power: 20 mW at 2.7 V, 38 mW at 5 V

Power-down to 10.8 μW

For convenience, the signal is internally ac-coupled. This

high-pass coupling, with a corner at approximately 0.016 GHz,

determines the lowest operating frequency. Therefore, the

source can be dc grounded.

The AD8315 provides a voltage output, VAPC, that has the

voltage range and current drive to directly connect to most

handset power amplifiers’ gain control pin. VAPC can swing

from 250 mV above ground to within 200 mV below the supply

voltage. Load currents of up to 6 mA can be supported.

APPLICATIONS

Single, dual, and triple band mobile handset (GSM, DCS, EDGE)

Transmitter power control

The setpoint control input is applied to the VSET pin and has

an operating range of 0.25 V to 1.4 V. The associated circuit

determines the slope and intercept of the linear-in-dB

measurement system; these are nominally 23 mV/dB and

−60 dBm for a 50 Ω termination (−73 dBV) at 0.9 GHz.

Further simplifying the application of the AD8315, the input

resistance of the setpoint interface is over 100 MΩ, and the bias

current is typically 0.5 μA.

GENERAL DESCRIPTION

The AD8315 is a complete low cost subsystem for the precise

control of RF power amplifiers operating in the frequency range

0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB.

It is intended for use in cellular handsets and other battery-

operated wireless devices. The log amp technique provides a

much wider measurement range and better accuracy than

controllers using diode detectors. In particular, its temperature

stability is excellent over a specified range of −30°C to +85°C.

The AD8315 is available in MSOP and LFCSP packages and

consumes 8.5 mA from a 2.7 V to 5.5 V supply. When powered

down, the sleep current is 4 μA.

FUNCTIONAL BLOCK DIAGRAM

VPOS

ENBL

LOW NOISE

BAND GAP

REFERENCE

OUTPUT

ENABLE

DELAY

LOW NOISE

GAIN BIAS

VAPC

×1.35

HI-Z

DET

LOW NOISE (25nV/√Hz)

RAIL-TO-RAIL BUFFER

RFIN

FLTR

VSET

10dB

V-I

23mV/dB

250mV TO

1.4V = 50dB

OFFSET

COMP’N

INTERCEPT

POSITIONING

COMM

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8315

TABLE OF CONTENTS

Features .............................................................................................. 1

Practical Loop............................................................................. 15

A Note About Power Equivalency ........................................... 16

Basic Connections...................................................................... 16

Range on VSET and RFIN ........................................................ 17

Transient Response .................................................................... 17

Mobile Handset Power Control Example ............................... 18

Enable and Power-On................................................................ 19

Input Coupling Options ............................................................ 19

Using the Chip Scale Package................................................... 20

Evaluation Board........................................................................ 20

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 12

Basic Theory................................................................................ 12

Controller-Mode Log Amps ..................................................... 13

Control Loop Dynamics............................................................ 13

REVISION HISTORY

Edit to Equation 11......................................................................... 10

Edits to Example section ............................................................... 10

Edit to Basic Connections Section............................................... 12

Edits to Input Coupling Options Section.................................... 14

Table III Becomes Table II............................................................. 15

Table II Recommended Components Deleted ........................... 15

Using the Chip-Scale Package Section Added............................ 15

Edits to Evaluation Board Section................................................ 15

Figure 12 Title Edited..................................................................... 16

Figure 13 Title Edited..................................................................... 16

8-Lead Chip Scale Package (CP-8) Added.................................. 17

Updated Outline Dimensions....................................................... 17

6/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Ordering Guide .......................................................... 23

1/03—Rev. 0 to Rev. B

Edits to Product Description Section ............................................ 1

Edit to Functional Block Diagram ................................................. 1

Edits to Specifications ...................................................................... 2

Edits to Absolute Maximum Ratings ............................................. 3

Ordering Guide Updated................................................................. 3

TPC 9 Replaced with New Figure .................................................. 5

Edits to TPC 27................................................................................. 8

Edit to Figure 1.................................................................................. 9

Edit to Figure 3................................................................................ 10

Edit to Equation 9........................................................................... 10

Edit to Equation 10......................................................................... 10

10/99—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD8315

SPECIFICATIONS

V_S= 2.7 V, T = 25°C, 52.3 Ω termination on RFIN, unless otherwise noted.

Table 1.

Parameter

Conditions

Min Typ

Max Unit

OVERALL FUNCTION

Frequency Range¹

Input Voltage Range

Equivalent ꢀdm Range

Logarithmic Slope²

Logarithmic Intercept²

Equivalent ꢀdm Level

RF INPUT INTERFACE

Input Resistance³

Input Capacitance³

OUTPUT

To meet all specifications

1 ꢀd log conformance, 0.1 GHz

0.1

−57

−44

21.5 24

−79 −70

−66 −57

2.5

−11 ꢀdV

+2 ꢀdm

25.5 mV/ꢀd

−64 ꢀdV

GHz

0.1 GH

0.1 GHz

−51 ꢀdm

Pin RFIN

0.1 GHz

2.8

0.9

kΩ

pF

Pin VAPC

Minimum Output Voltage

V_SET≤ 200 mV, ENdL high

ENdL low

R_L≥ 800 Ω

85°C, V_POS= 3 V, I_OUT= 6 mA

2.7 V ≤ V_POS≤ 5.5 V, R_L= ∞

Source/Sink

0.25 0.27

0.02

2.45

0.3

2.6

V

Maximum Output Voltage

vs. Temperature⁴

General Limit

Output Current Drive

Output duffer Noise

Output Noise

Small Signal danꢀwiꢀth

Slew Rate

2.54

V_POS− 0.1

5/200

25

130

30

13

V

mA/μA

nV√Hz

nV/√Hz

MHz

V/μs

ns

RF input = 2 GHz, 0 ꢀdm, f_NOISE= 100 kHz, C_FLT= 220 pF

0.2 V to 2.6 V swing

10% to 90%, 1.2 V step (V_SET), open loop⁵

Response Time

FLTR = open, see Figure 26

150

SETPOINT INTERFACE

Nominal Input Range

Logarithmic Scale Factor

Input Resistance

Pin VSET

Corresponꢀing to central 50 ꢀd

0.25

1.8

1.4

V

ꢀd/V

kΩ

43.5

100

16

Slew Rate

V/μs

ENAdLE INTERFACE

Logic Level to Enable Power

Pin ENdL

V_POS

V

Input Current when Enable

High

20

μA

Logic Level to Disable Power

Enable Time

0.8

5

V

μs

Time from ENdL high to V_APCwithin 1% of final value,

V_SET≤ 200 mV, refer to Figure 23

4

Disable Time

Time from ENdL low to V_APCwithin 1% of final value,

V_SET≤ 200 mV, refer to Figure 23

Time from VPOS/ENdL high to V_APCwithin 1% of final value,

8

9

μs

ns

Power-On/Enable Time

2

3

V

_SET≤ 200 mV, refer to Figure 28

Time from VPOS/ENdL low to V_APCwithin 1% of final value,

V_SET≤ 200 mV, refer to Figure 28

100

200

Rev. C | Page 3 of 24

AD8315

Parameter

Conditions

Min Typ

Max Unit

5.5

10.7 mA

12.9 mA

POWER INTERFACE

Supply Voltage

Quiescent Current

Over Temperature

Disable Current⁶

Over Temperature

Pin VPOS

2.7

8.5

V

ENdL high

−30°C ≤ T_A≤ +85°C

ENdL low

4

10

13

μA

−30°C ≤ T_A≤ +85°C

¹Operation ꢀown to 0.02 GHz is possible.

²Mean anꢀ stanꢀarꢀ ꢀeviation specifications are available in Table 2

³See Figure 11 for plot of input impeꢀance vs. frequency.

⁴This parameter is guaranteeꢀ but not testeꢀ in proꢀuction. Limit is −3 sigma from the mean.

⁵Response time in a closeꢀ-loop system ꢀepenꢀs on the filter capacitor (C_FLT) useꢀ anꢀ the response of the variable gain element.

⁶This parameter is guaranteeꢀ but not testeꢀ in proꢀuction. Maximum specifieꢀ limit on this parameter is the 6 sigma value.

Table 2. Typical Specifications at Selected Frequencies at 25°C (Mean and Sigma)

1 dB Dynamic Range

Low Point (dBV) High Point (dBV)

Slope (mV/dB)

Intercept (dBV)

Frequency (GHz)

Mean

23.8

23.2

22.2

22.3

Sigma

Mean

−70.1

−72.6

−73.8

−75.6

Sigma

Mean

Sigma

1.3

0.9

1.1

Mean

Sigma

0.8

1.7

0.1

0.9

1.9

2.5

0.3

0.4

0.3

0.4

1.8

1.6

1.5

−57.7

−61.0

−62.9

−64.0

−10.6

−11.2

−18.5

−20.0

Rev. C | Page 4 of 24

AD8315

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Supply Voltage VPOS

Temporary Overvoltage VPOS

(100 cycles, 2 sec ꢀuration, ENdL Low)

VAPC, VSET, ENdL

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

5.5 V

6.3 V

0 V, V_POS

17 ꢀdm

1.6 V rms

60 mW

200°C/W

80°C/W

200°C/W

125°C

−40°C to +85°C

−65°C to +150°C

RFIN

Equivalent Voltage

Internal Power Dissipation

θ_JA(MSOP)

θ_JA(LFCSP, Paꢀꢀle Solꢀereꢀ)

θ_JA(LFCSP, Paꢀꢀle Not Solꢀereꢀ)

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

Leaꢀ Temperature (Solꢀering 60 sec)

MSOP

300°C

240°C

LFCSP

ESD CAUTION

ESD (electrostatic ꢀischarge) sensitive ꢀevice. Electrostatic charges as high as 4000 V reaꢀily accumulate on the

human boꢀy anꢀ test equipment anꢀ can ꢀischarge without ꢀetection. Although this proꢀuct features

proprietary ESD protection circuitry, permanent ꢀamage may occur on ꢀevices subjecteꢀ to high energy

electrostatic ꢀischarges. Therefore, proper ESD precautions are recommenꢀeꢀ to avoiꢀ performance

ꢀegraꢀation or loss of functionality.

Rev. C | Page 5 of 24

AD8315

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

8

7

6

5

RFIN

ENBL

VSET

FLTR

VPOS

VAPC

NC

AD8315

TOP VIEW

(Not to Scale)

COMM

NC = NO CONNECT

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

7

8

RFIN

ENdL

VSET

FLTR

COMM

NC

RF Input.

Connect to VPOS for Normal Operation Connect Pin to Grounꢀ for Disable Moꢀe.

Setpoint Input. Nominal input range 0.25 V to 1.4 V.

Integrator Capacitor. Connect between FLTR anꢀ COMM.

Device Common (Grounꢀ).

No Connection.

Output. Control voltage for gain control element.

Positive Supply Voltage: 2.7 V to 5.5 V.

VAPC

VPOS

Rev. C | Page 6 of 24

AD8315

TYPICAL PERFORMANCE CHARACTERISTICS

4

3

23

10

13

0

2.5GHz

3

–10

–20

–30

2

1

1.9GHz

0.9GHz

0.1GHz

–7

0.1GHz

–17

–27

–37

–47

0

–40

–50

–60

–70

–80

–1

–2

0.9GHz

2.5GHz

1.9GHz

–3

–4

–57

–67

0.2

0.4

0.6

0.8

V

1.0

(V)

1.2

1.4

1.6

0.2

0.4

0.6

0.8

V

1.0

1.2

1.4

SET

(V)

SET

Figure 6. Log Conformance vs. V_SET

Figure 3. Input Amplitude vs. V_SET

10

0

4

3

10

0

4

–30°C

+25°C

3

2

(+3dBm)

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

2

+85°C

–30°C

1

+85°C

0

+25°C

–1

–2

–3

–4

–1

–2

+25°C

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

(–47dBm)

–60

–70

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

–3

–4

–60

–70

(–47dBm)

+85°C

SLOPE AND INTERCEPT AT +25°C

0.7 0.9 1.1 1.3

(V)

–30°C

0.1

0.3

0.5

0.7

0.9

(V)

1.1

1.3

1.5

0.1

0.3

0.5

1.5

V

SET

Figure 7. Input Amplitude and Log Conformance vs. V_SETat 1.9 GHz

Figure 4. Input Amplitude and Log Conformance vs. V_SETat 0.1 GHz

10

0

4

3

10

0

4

+85°C

3

–30°C

+25°C

(+3dBm)

2

–10

–20

–30

–40

–50

(+3dBm)

–10

–20

–30

–40

–50

2

–30°C

+85°C

–30°C

+85°C

+25°C

1

0

+25°C

–30°C

–1

–2

–3

–4

–1

–2

+25°C

+85°C

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

(–47dBm)

–60

–70

(–47dBm)

–3

–4

–60

–70

0.1

0.3

0.5

0.7

0.9

(V)

1.1

1.3

1.5

0.1

0.3

0.5

0.7

0.9

(V)

1.1

1.3

1.5

V

SET

Figure 5. Input Amplitude and Log Conformance vs. V_SETat 0.9 GHz

Figure 8. Input Amplitude and Log Conformance vs. V_SETat 2.5 GHz

Rev. C | Page 7 of 24

AD8315

4

3

–30°C

+85°C

3

2

1

0

–1

–2

–3

–1

–2

–3

–4

+85°C

–30°C

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

–4

–80

–70

–60

–50

RF INPUT AMPLITUDE (dBV)

(–47dBm)

–40

–30

–20

–10

0

–80

–70

–60

RF INPUT AMPLITUDE (dBV)

(–47dBm)

–50

–40

–30

–20

–10

0

(+3dBm)

Figure 9. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.1 GHz

Figure 12. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 1.9 GHz

4

3

–30°C

2

1

2

1

0

–1

+85°C

–30°C

–2

+85°C

ERROR AT +85°C AND –30°C

–3

ERROR AT +85°C AND –30°C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

–3

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25°C

–4

–80

–70

–60

RF INPUT AMPLITUDE (dBV)

(–47dBm)

–50

–40

–30

–20

–10

0

–80

–70

–60

–50

RF INPUT AMPLITUDE (dBV)

(–47dBm)

–40

–30

–20

–10

0

(+3dBm)

Figure 10. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 0.9 GHz

Figure 13. Distribution of Error at Temperature After Ambient Normalization vs.

Input Amplitude, 3 Sigma to Either Side of Mean, 2.5 GHz

0

3000

2700

2400

2100

1800

1500

1200

900

600

300

0

10

–200

–400

–600

–800

–1000

–1200

–1400

–1600

–1800

–2000

8

CHIP SCALE (LFCSP)

FREQUENCY MSOP

(GHz)

0.1

0.9

1.9

R

– jXΩ

R – jXΩ

2900 – j1900

700 – j240

130 – j80

2700 – j1500

730 – j220

460 – j130

440 – j110

6

4

X (LFCSP)

170 – j70

2.5

R

X

DECREASING

INCREASING

X (MSOP)

V

ENBL

R (LFCSP)

2

0

R (MSOP)

1.3

1.4

1.5

1.6

1.7

0

0.5

1.0

1.5

2.0

2.5

V

(V)

FREQUENCY (GHz)

ENBL

Figure 11. Input Impedance

Figure 14. Supply Current vs. V_ENBL

Rev. C | Page 8 of 24

AD8315

25

24

–66

–68

–70

–72

–74

–76

–78

–80

+85°C

+25°C

23

22

21

20

+25°C

–30°C

0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

FREQUENCY (GHz)

Figure 18. Intercept vs. Frequency; −30°C, +25°C, and +85°C

Figure 15. Slope vs. Frequency; −30°C, +25°C, and +85°C

–68

24

23

22

21

0.1GHz

0.9GHz

0.1GHz

–70

–72

0.9GHz

–74

–76

–78

–80

1.9GHz

2.5GHz

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

S

Figure 16. Slope vs. Supply Voltage

Figure 19. Intercept vs. Supply Voltage

10000

1000

100

45

40

35

0

C

= 220pF, RF INPUT = 2GHz

FLT

–10

C

= 0pF

FLT

–20

RF INPUT

–51dBV

30

–30

–40

25

20

–50

–48dBV

–33dBV

–43dBV

–60

15

–70

10

–80

5

–90

0

–23dBV

–100

–110

–120

–130

–5

–13dBV

–10

–15

–20

–25

–30

–35

–40

C

= 220pF

FLT

–53dBV AND

–63dBV

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 17. AC Response from VSET to VAPC

Figure 20. VAPC Noise Spectral Density

Rev. C | Page 9 of 24

AD8315

2.8

2.7

2.6

2.5

2.4

3.5

3.3

3.1

2.9

2.7

2.5

2mA

0mA

4mA

6mA

SHADING INDICATES

±3 SIGMA

2.3

2.7

2.8

2.9

3.0

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

SUPPLY VOLTAGE (V)

SUPPLYVOLTAGE (V)

Figure 21. Maximum V_APCVoltage vs. Supply Voltage by Load Current

Figure 24. Maximum V_APCVoltage vs. Supply Voltage with 4 mA Load Current

AVERAGE = 16 SAMPLES

V

APC

200mV PER VERTICAL

DIVISION

1V PER

VERTICAL

DIVISION

V

APC

GND

2µs PER

HORIZONTAL

DIVISION

PULSED RF

0.1GHz, –13dBV

1V PER

VERTICAL

DIVISION

RF

INPUT

100ns PER

HORIZONTAL

DIVISION

V

ENBL

Figure 22. ENBL Response Time

Figure 25. V_APCResponse Time, Full-Scale Amplitude Change, Open-Loop

10MHz REF

OUTPUT

R AND S SMT03

SIGNAL

GENERATOR

PULSE

MODULATION

MODE

TRIG

OUT

10MHz REF

OUTPUT

R AND S

SMT03

SIGNAL

STANFORD DS345

PULSE

GENERATOR

EXTTRIG

OUT

TIMEBASE

PICOSECOND

PULSE LABS

PULSE

TRIG

OUT

PULSE MODE IN

GENERATOR

PULSE OUT

RF OUT

PULSE OUT

RF OUT

RF

2.7V

SPLITTER

–3dB

2.7V

TEK P6205

FET PROBE

0.1µF

AD8315

TRIG

1

2

3

4

8

VPOS

VAPC

NC

AD8315

RFIN

ENBL

VSET

FLTR

TRIG

1

2

3

4

8

VPOS

VAPC

NC

RFIN

ENBL

VSET

FLTR

52.3Ω

TEK P6205

FET PROBE

TEK TDS694C

SCOPE

7

6

5

52.3Ω

TEK P6205

FET PROBE

TEKTDS694C

SCOPE

7

6

5

2.7V

0.3V

COMM

NC

220pF

NC = NO CONNECT

Figure 23. Test Setup for ENBL Response Time

Figure 26. Test Setup for VAPC Response Time

Rev. C | Page 10 of 24

AD8315

AVERAGE = 16 SAMPLES

500mV PER

VERTICAL

DIVISION

V

APC

200mV PER

GND

V

VERTICAL

DIVISION

APC

GND

1V PER

VERTICAL

DIVISION

2µs PER

HORIZONTAL

DIVISION

2µs PER

HORIZONTAL

DIVISION

1V PER

VERTICAL

DIVISION

V

AND

S

V

ENBL

V

S

GND

AVERAGE = 16 SAMPLES

Figure 29. Power-On and Power-Off Response with VSET and ENBL Grounded

Figure 27. Power-On and Power-Off Response with VSET Grounded

TRIG

OUT

10MHz REF

OUTPUT

10MHz REF

OUTPUT

TRIG

OUT

R AND S

SMT03

SIGNAL

R AND S

SMT03

SIGNAL

STANFORD DS345

PULSE

GENERATOR

STANFORD DS345

PULSE

GENERATOR

EXTTRIG

GENERATOR

PULSE OUT

RF OUT

AD811

49.9Ω

732Ω

AD8315

TEK P6205

FET PROBE

TEK P6205

FET PROBE

1

2

3

4

8

7

6

5

1

2

3

4

VPOS

VAPC

NC

8

7

6

5

RFIN

ENBL

VSET

FLTR

VPOS

VAPC

NC

RFIN

ENBL

VSET

FLTR

TRIG

52.3Ω

TEKTDS694C

SCOPE

TEK P6205

FET PROBE

TEKTDS694C

SCOPE

TEK P6205

FET PROBE

COMM

220pF

NC = NO CONNECT

Figure 30. Test Setup for Power-On and Power-Off Response with VSET

and ENBL Grounded

Figure 28. Test Setup for Power-On and Power-Off Response with VSET Grounded

Rev. C | Page 11 of 24

AD8315

THEORY OF OPERATION

when the net resistive part of the input impedance of the log

amp is 50 Ω. However, both the slope and the intercept are

dependent on frequency (see Figure 15 and Figure 18).

The AD8315 is a wideband logarithmic amplifier (log amp)

similar in design to the AD8313 and AD8314. However, it is

strictly optimized for use in power control applications rather

than as a measurement device. Figure 31 shows the main

features in block schematic form. The output (Pin 7, VAPC) is

intended to be applied directly to the automatic power-control

(APC) pin of a power amplifier module.

Keeping in mind that log amps do not respond to power but

only to voltages and that the calibration of the intercept is

waveform dependent and is only quoted for a sine wave signal,

the equivalent power response can be written as

BASIC THEORY

V_OUT= V_DB(P_IN− P_Z)

where:

(2)

Logarithmic amplifiers provide a type of compression in which

a signal having a large range of amplitudes is converted to one

of smaller range. The use of the logarithmic function uniquely

results in the output representing the decibel value of the input.

The fundamental mathematical form is:

P_IN, the input power, and P_Z, the equivalent intercept, are both

expressed in dBm (thus, the quantity in parentheses is simply a

number of decibels).

V_IN

V_Z

V_DBis the slope expressed as so many mV/dB.

V_OUT=V_SLPlog₁₀

(1)

For a log amp having a slope V_DBof 24 mV/dB and an intercept

at −57 dBm, the output voltage for an input power of –30 dBm

is 0.024 [−30 − (−57)] = 0.648 V.

Here V_INis the input voltage, V_Zis called the intercept (voltage)

because when V_IN= V_Zthe argument of the logarithm is unity

and thus the result is zero, and V_SLPis called the slope (voltage),

which is the amount by which the output changes for a certain

change in the ratio (V_IN/V_Z). When BASE-10 logarithms are

used, denoted by the function log₁₀, V_SLPrepresents the volts/

decade, and since a decade corresponds to 20 dB, V_SLP/20

represents the volts/dB. For the AD8315, a nominal (low

frequency) slope of 24 mV/dB was chosen, and the intercept V_Z

was placed at the equivalent of −70 dBV for a sine wave input

(316 μV rms). This corresponds to a power level of −57 dBm

Further details about the structure and function of log amps can

be found in data sheets for other log amps produced by Analog

Devices, Inc. Refer to the AD640 data sheet and AD8307 data

sheet, both of which include a detailed discussion of the basic

principles of operation and explain why the intercept depends

on waveform, an important consideration when complex

modulation is imposed on an RF carrier.

(PRECISE GAIN

CONTROL)

(PRECISE SLOPE

CONTROL)

(ELIMINATES

GLITCH)

VPOS

ENBL

LOW NOISE

BAND GAP

REFERENCE

OUTPUT

ENABLE

DELAY

LOW NOISE

GAIN BIAS

(CURRENT-MODE SIGNAL)

DET

VAPC

×1.35

HI-Z

DET

LOW NOISE (25nV/√Hz)

RAIL-TO-RAIL BUFFER

RFIN

FLTR

VSET

10dB

(CURRENT-

NULLING

MODE)

(CURRENT-MODE

FEEDBACK)

V-I

23mV/dB

250mV TO

1.4V = 50dB

OFFSET

COMP’N

INTERCEPT

POSITIONING

(SMALL INTERNAL

FILTER CAPACITOR

FOR GHz RIPPLE)

COMM

(PADDLE)

(WEAK GM STAGE)

Figure 31. Block Schematic

Rev. C | Page 12 of 24

AD8315

In a device intended for measurement applications, this current

would then be converted to an equivalent voltage, to provide the

log (V_IN) function shown in Equation 1. However, the design of

the AD8315 differs from standard practice in that its output

needs to be a low noise control voltage for an RF power amplifier

not a direct measure of the input level. Furthermore, it is highly

desirable that this voltage be proportional to the time integral of

the error between the actual input V_INand the dc voltage V_SET

(applied to Pin 3, VSET) that defines the setpoint, that is, a

target value for the power level, typically generated by a DAC.

The intercept need not correspond to a physically realizable

part of the signal range for the log amp. Therefore, the specified

intercept is −70 dBV, at 0.1 GHz, whereas the smallest input for

accurate measurement (a +1 dB error, see Table 2) at this

frequency is higher, being about −58 dBV. At 2.5 GHz, the

+1 dB error point shifts to −64 dBV. This positioning of the

intercept is deliberate and ensures that the V_SETvoltage is within

the capabilities of certain DACs, whose outputs cannot swing

below 200 mV. Figure 32 shows the 100 MHz response of the

AD8315; the vertical axis does not represent the output (at pin

VAPC) but the value required at the power control pin, VSET,

to null the control loop.

This is achieved by converting the difference between the sum

of the detector outputs (still in current form) and an internally

generated current proportional to V_SETto a single-sided,

current-mode signal. This, in turn, is converted to a voltage (at

Pin 4, FLTR, the low-pass filter capacitor node) to provide a

close approximation to an exact integration of the error between

the power present in the termination at the input of the AD8315

and the setpoint voltage. Finally, the voltage developed across

the ground-referenced filter capacitor C_FLTis buffered by a

special low noise amplifier of low voltage gain (×1.35) and

presented at Pin 7 (VAPC) for use as the control voltage for the

RF power amplifier. This buffer can provide rail-to-rail swings

and can drive a substantial load current, including large

capacitors. Note that the RF power amplifier is assumed to have

a positive slope with RF power increasing monotonically with

an increasing APC control voltage.

1.5

1.416V @ –11dBV

1.0

ACTUAL

0.5

0.288V @ –58dBV

–70dBV

IDEAL

0

100µV

–80dBV

–67dBm

1mV

–60dBV

–47dBm

10mV

–40dBV

–27dBm

100mV

–20dBV

–7dBm

1V (RMS)

0dBV

+13dBm (RE 50Ω)

V

, dBV , P

IN IN IN

CONTROL LOOP DYNAMICS

Figure 32. Basic Calibration of the AD8315 at 0.1 GHz

To understand how the AD8315 behaves in a complete control

loop, an expression for the current in the integration capacitor

as a function of the input V_INand the setpoint voltage V_SETmust

be developed (see Figure 33).

CONTROLLER-MODE LOG AMPS

The AD8315 combines the two key functions required for the

measurement and control of the power level over a moderately

wide dynamic range. First, it provides the amplification needed

to respond to small signals in a chain of four amplifier/limiter

cells (see Figure 31), each having a small signal gain of 10 dB

and a bandwidth of approximately 3.5 GHz. At the output of

each of these amplifier stages is a full-wave rectifier, essentially a

square law detector cell that converts the RF signal voltages to a

fluctuating current having an average value that increases with

signal level. A further passive detector stage is added before the

first stage. These five detectors are separated by 10 dB, spanning

some 50 dB of dynamic range. Their outputs are each in the

form of a differential current, making summation a simple

matter. It is readily shown that the summed output can closely

approximate a logarithmic function. The overall accuracy at the

extremes of this total range, viewed as the deviation from an

ideal logarithmic response, that is, the log conformance error,

can be judged by referring to Figure 6, which shows that errors

across the central 40 dB are moderate. Other performance

curves show how conformance to an ideal logarithmic function

varies with supply voltage, temperature, and frequency.

V

SET

I

= V /4.15kΩ

SET

SETPOINT

INTERFACE

3

V

SET

FLTR

VAPC

7

RFIN

1

LOGARITHMIC

RF DETECTION

SUBSYSTEM

×1.35

4

V

I

ERR

IN

DET

C

FLT

I

= I

SLP

log (V /V )

10 IN

DET

Z

Figure 33. Behavioral Model of the AD8315

Rev. C | Page 13 of 24

AD8315

First, the summed detector currents are written as a function of

the input

Equation 6 can be restated as

V_SET−V_SLPlog₁₀

(

V_INV_Z

)

V_APC

(

s

)

=

(7)

I_DET= I_SLPlog₁₀(V_IN/V_Z)

where:

(3)

sT

where V_SLPis the volts-per-decade slope from Equation 1,

having a value of 480 mV/decade, and T is an effective time

constant for the integration, being equal to 4.15 kΩ × C_FLT/1.35;

the resistor value comes from the setpoint interface scaling

Equation 4 and the factor 1.35 arises because of the voltage gain

of the buffer. Therefore, the integration time constant can be

written as

I_DETis the partially filtered demodulated signal, whose

exact average value is extracted through the subsequent

integration step.

I_SLPis the current-mode slope and has a value of 115 μA per

decade (that is, 5.75 μA/dB).

V_INis the input in V rms.

T = 3.07 C_FLTin μs, when C is expressed in nF

(8)

V_Zis the effective intercept voltage, which, as previously noted,

is dependent on waveform but is 316 μV rms (−70 dBV) for a

sine wave input.

To simplify our understanding of the control loop dynamics,

begin by assuming that the power amplifier gain function is

actually linear in dB, and for the moment, use voltages to

express the signals at the power amplifier input and output.

Now the current generated by the setpoint interface is simply

I_SET(4)= V_SET/415 kΩ

(4)

Let the RF output voltage be V_PAand let its input be V_CW

.

Furthermore, to characterize the gain control function, this

form is used

The difference between this current and I_DETis applied to the

loop filter capacitor C_FLT. It follows that the voltage appearing

on this capacitor, V_FLT, is the time integral of the difference

current:

V_PA= G_OV_CW10⁽^V

(9)

V

)

APC GBC

where:

V_FLT(s) = (I_SET− I_DET)/sC_FLT

(5)

(6)

G_Ois the gain of the power amplifier when V_APC= 0.

V_GBCis the gain scaling.

V_SET4.15 kꢀ − I_SLPlog₁₀

(

V_INV_Z

)

=

sC_FLT

While few amplifiers conform so conveniently to this law, it

provides a clearer starting point for understanding the more

complex situation that arises when the gain control law is less ideal.

The control output V_APCis slightly greater than this, because the

gain of the output buffer is ×1.35. In addition, an offset voltage

is deliberately introduced in this stage; this is inconsequential

because the integration function implicitly allows for an

arbitrary constant to be added to the form of Equation 6. The

polarity is such that V_APCrises to its maximum value for any

value of V_SETgreater than the equivalent value of V_IN. In

practice, the V_APCoutput rails to the positive supply under this

condition unless the control loop through the power amplifier

is present. In other words, the AD8315 seeks to drive the RF

power to its maximum value whenever it falls below the

setpoint. The use of exact integration results in a final error that

is theoretically 0, and the logarithmic detection law would

ideally result in a constant response time following a step

change of either the setpoint or the power level, if the power-

amplifier control function were likewise linear in dB. However,

this latter condition is rarely true, and it follows that in practice,

the loop response time depends on the power level, and this

effect can strongly influence the design of the control loop.

This idealized control loop is shown in Figure 34. With some

manipulation, it is found that the characteristic equation of this

system is

(

V_SETV_GBC

)

V_SLP−V_GBClog₁₀

1 + sT_O

(

kG_OV_CWV_Z

)

(10)

V_APC

(

s

)

=

where:

k is the coupling factor from the output of the power amplifier

to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler).

T_Ois a modified time constant (V_GBC/V_SLP)T.

This is quite easy to interpret. First, it shows that a system of

this sort exhibits a simple single-pole response, for any power

level, with the customary exponential time domain form for

either increasing or decreasing step polarities in the demand

level V_SETor the carrier input V_CW. Second, it reveals that the

final value of the control voltage V_APCis determined by several

fixed factors:

V_APC

(

τ = ∞

)

=

(

V_SETV_GBC

)

V_SLP− log₁₀

(

kG_OV_CWV_Z(11)

)

Rev. C | Page 14 of 24

AD8315

Example

Assume that the gain magnitude of the power amplifier runs

from a minimum value of ×0.316 (−10 dB) at V_APC= 0 to ×100

(40 dB) at V_APC= 2.5 V. Applying Equation 9, G_O= 0.316 and

V_GBC= 1 V. Using a coupling factor of k = 0.0316 (that is, a

30 dB directional coupler) and recalling that the nominal value

of V_SLPis 480 mV and V_Z= 316 μV for the AD8315, first calculate

the range of values needed for V_SETto control an output range of

+33 dBm to −17 dBm. This can be found by noting that, in the

steady state, the numerator of Equation 7 must be 0, that is:

V

DIRECTIONAL COUPLER

CW

RF

RF PA

RF DRIVE: UP

TO 2.5GHz

V

= kV

RF

IN

V

AD8315

APC

V

SET

RESPONSE-SHAPING

OF OVERALL CONTROL-

LOOP (EXTERNAL CAP)

C

FLT

Figure 34. Idealized Control Loop for Analysis

V_SET= V_SLPlog₁₀(kV_PA/V_Z)

(12)

Finally, using the loop time constant for these parameters and

an illustrative value of 2 nF for the filter capacitor C_FLT

where V_INis expanded to kV_PA, the fractional voltage sample of

the power amplifier output. For 33 dBm, V_PA= 10 V rms, which

evaluates to

T_O= (V_GBC/V_SLP) T

V_SET(max) = 0.48 log₁₀(316 mV/316 μV) = 1.44 V

(13)

= (1/0.48)3.07 μs × 2 (nF) = 12.8 μs

(17)

For a delivered power of −17 dBm, V_PA= 31.6 mV rms

PRACTICAL LOOP

V_SET(min) = 0.48 log₁₀(1 mV/316 μV) = 0.24 V

(14)

At present time, power amplifiers, or VGAs preceding such

amplifiers, do not provide an exponential gain characteristic. It

follows that the loop dynamics (the effective time constant)

varies with the setpoint because the exponential function is

unique in providing constant dynamics. The procedure must

therefore be as follows. Beginning with the curve usually provided

for the power output vs. the APC voltage, draw a tangent at the

point on this curve where the slope is highest (see Figure 35).

Using this line, calculate the effective minimum value of the

variable V_GBCand use it in Equation 17 to determine the time

constant. Note that the minimum in V_GBCcorresponds to the

Check that the power range is 50 dB, which should correspond

to a voltage change in V_SETof 50 dB × 24 mV/dB = 1.2 V,

which agrees.

Now, the value of V_APCis of interest, although it is a dependent

parameter, inside the loop. It depends on the characteristics of

the power amplifier, and the value of the carrier amplitude V_CW

Using the control values previously derived, that is, G_O= 0.316

and V_GBC= 1 V, and assuming the applied power is fixed at

−7 dBm (so V_CW= 100 mV rms), the following is true using

Equation 11

.

maximum rate of change in the output power vs. V_APC

.

V_APC(max) = (V_SETV_GBC)/V_SLP− log₁₀kG_OV_CW/V_Z

For example, suppose it is found that, for a given drive power,

the amplifier generates an output power of P₁at V_APC= V₁and

P₂at V_APC= V₂. Then, it is readily shown that

= (1.44 × 1)/0.48 − log₁₀(0.0316 × 0.316 × 0.1/316 μV)

= 3.0 − 0.5 = 2.5 V

(15)

(16)

V

_GBC= 20 (V₂− V₁)/(P₂− P₁)

(18)

V_APC(min) = (V_SETV_GBC)/V_SLP− log₁₀kG_OV_CW/V_Z

This should be used to calculate the filter capacitance. The

= (0.24 × 1)/0.48 − log₁₀(0.0316 × 0.316 × 0.1/316 μV)

= 0.5 − 0.5 = 0

response time at high and low power levels (on the shoulders

of the curve shown in Figure 35) is slower. Note also that it is

sometimes useful to add a 0 in the closed-loop response by

placing a resistor in series with C_FLT. For more information on

this, see the Transient Response section.

both of which results are consistent with the assumptions made

about the amplifier control function. Note that the second term

is independent of the delivered power and a fixed function of

the drive power.

Rev. C | Page 15 of 24

AD8315

V , P

2

The logarithmic slope, V_SLPin Equation 1, which is the amount

by which the setpoint voltage needs to be changed for each

decibel of input change (voltage or power), is, in principle,

independent of waveform or termination impedance. In

practice, it usually falls off somewhat at higher frequencies,

due to the declining gain of the amplifier stages and other

effects in the detector cells (see Figure 15).

33

23

13

3

BASIC CONNECTIONS

Figure 36 shows the basic connections for operating the

AD8315, and Figure 37 shows a block diagram of a typical

application. The AD8315 is typically used in the RF power

control loop of a mobile handset.

–7

0

0.5

1.0

1

1.5

2.0

2.5

V , P

1

V

(V)

APC

A supply voltage of 2.7 V to 5.5 V is required for the AD8315.

The supply to the VPOS pin should be decoupled with a low

inductance 0.1 μF surface-mount ceramic capacitor, close to the

device. The AD8315 has an internal input coupling capacitor.

This negates the need for external ac coupling. This capacitor,

along with the low frequency input impedance of the device of

approximately 2.8 kΩ, sets the minimum usable input frequency to

around 0.016 GHz. A broadband 50 Ω input match is achieved

in this example by connecting a 52.3 Ω resistor between RFIN

and ground. A plot of input impedance vs. frequency is shown

in Figure 11. Other coupling methods are also possible (see

Input Coupling Options section).

Figure 35. Typical Power-Control Curve

A NOTE ABOUT POWER EQUIVALENCY

In using the AD8315, it must be understood that log amps do

not fundamentally respond to power. It is for this reason that

dBV (decibels above 1 V rms) are used rather than the commonly

used metric of dBm. The dBV scaling is fixed, independent of

termination impedance, while the corresponding power level is

not. For example, 224 mV rms is always −13 dBV (with one

further condition of an assumed sinusoidal waveform; see the

AD640 data sheet for more information about the effect of

waveform on logarithmic intercept), and this corresponds to a

power of 0 dBm when the net impedance at the input is 50 Ω.

When this impedance is altered to 200 Ω, however, the same

voltage corresponds to a power level that is four times smaller

(P = V²/R) or −6 dBm. A dBV level can be converted to dBm in

the special case of a 50 Ω system and a sinusoidal signal by

simply adding 13 dB (0 dBV is then, and only then, equivalent

to 13 dBm).

C1

0.1µF

R1

52.3Ω

AD8315

1

2

3

4

8

7

6

5

+V

S

RFIN

VPOS

VAPC

NC

RFIN

ENBL

VSET

FLTR

(2.7V TO 5.5V)

+V

S

+V

APC

V

SET

COMM

C

FLT

NC = NO CONNECT

Therefore, the external termination added ahead of the AD8315

determines the effective power scaling. This often takes the

form of a simple resistor (52.3 Ω provides a net 50 Ω input), but

more elaborate matching networks can be used. The choice of

impedance determines the logarithmic intercept, that is, the

input power for which the V_SETvs. P_INfunction would cross the

baseline if that relationship were continuous for all values of

V_IN. This is never the case for a practical log amp; the intercept

(so many dBV) refers to the value obtained by the minimum

error straight line fit to the actual graph of V_SETvs. P_IN(more

generally, V_IN). Where the modulation is complex, as in CDMA,

the calibration of the power response needs to be adjusted; the

intercept remains stable for any given arbitrary waveform.

When a true power (waveform independent) response is

needed, a mean-responding detector, such as the AD8361,

should be considered.

Figure 36. Basic Connections

POWER

AMP

DIRECTIONAL

COUPLER

RFIN

ATTENUATOR

GAIN

CONTROL

VOLTAGE

VAPC

AD8315

VSET

DAC

RFIN

52.3Ω

FLTR

C

FLT

Figure 37. Typical Application

Rev. C | Page 16 of 24

AD8315

In a power control loop, the AD8315 provides both the detector

and controller functions. A sample of the power amplifier’s (PA)

output power is coupled to the RF input of the AD8315, usually

via a directional coupler. In dual-mode applications, where

there are two PAs and two directional couplers, the outputs of

the directional couplers can be passively combined (both PAs

will never be turned on simultaneously) before being applied to

the AD8315.

Above 250 mV, V_SEThas a linear control range up to 1.4 V,

corresponding to a dynamic range of 50 dB. This results in a

slope of 23 mV/dB or approximately 43.5 dB/V.

TRANSIENT RESPONSE

The time domain response of power amplifier control loops,

using any kind of controller, is only partially determined by the

choice of filter, which, in the case of the AD8315, has a true

integrator form 1/sT, as shown in Equation 7, with a time

constant given by Equation 8. The large signal step response is

also strongly dependent on the form of the gain-control law.

Nevertheless, some simple rules can be applied. When the filter

capacitor C_FLTis very large, it dominates the time domain

response, but the incremental bandwidth of this loop still varies

as V_APCtraverses the nonlinear gain-control function of the PA,

as shown in Figure 35. This bandwidth is highest at the point

where the slope of the tangent drawn on this curve is greatest,

that is, for power outputs near the center of the PA’s range, and

is much reduced at both the minimum and the maximum

power levels, where the slope of the gain control curve is lowest

due to its S-shaped form.

A setpoint voltage is applied to VSET from the controlling

source (generally, this is a DAC). Any imbalance between the

RF input level and the level corresponding to the setpoint

voltage is corrected by the AD8315’s VAPC output that drives

the gain control terminal of the PA. This restores a balance

between the actual power level sensed at the input of the

AD8315 and the value determined by the setpoint. This

assumes that the gain control sense of the variable gain

element is positive, that is, an increasing voltage from

VAPC tends to increase gain.

V_APCcan swing from 250 mV to within 100 mV of the supply

rail and can source up to 6 mA. If the control input of the PA

needs to source current, a suitable load resistor can be connected

between VAPC and COMM. The output swing and current

sourcing capability of VAPC is shown in Figure 21.

Using smaller values of C_FLT, the loop bandwidth generally

increases in inverse proportion to its value. Eventually, however,

a secondary effect appears due to the inherent phase lag in the

power amplifier’s control path, some of which can be due to

parasitic or deliberately added capacitance at the VAPC pin.

This results in the characteristic poles in the ac loop equation

moving off the real axis and thus becoming complex (and

somewhat resonant). This is a classic aspect of control loop

design. The lowest permissible value of C_FLTneeds to be determined

experimentally for a particular amplifier. For GSM and DCS

power amplifiers, C_FLTtypically ranges from 150 pF to 300 pF.

RANGE ON VSET AND RFIN

The relationship between the RF input level and the setpoint

voltage follows from the nominal transfer function of the device

(see Figure 4, Figure 5, Figure 7, and Figure 8). At 0.9 GHz, for

example, a voltage of 1 V on VSET indicates a demand for

−30 dBV (−17 dBm, re 50 Ω) at RFIN. The corresponding power

level at the output of the power amplifier is greater than this

amount due to the attenuation through the directional coupler.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistance in series

with C_FLT; this generates an additional 0 in the closed-loop

transfer function, that serves to cancel some of the higher order

poles in the overall loop. A combination of main capacitor C_FLT

shunted by a second capacitor and resistor in series is also

useful in minimizing the settling time of the loop.

For setpoint voltages of less than approximately 250 mV, V_APC

remains unconditionally at its minimum level of approximately

250 mV. This feature can be used to prevent any spurious

emissions during power-up and power-down phases.

Rev. C | Page 17 of 24

AD8315

3.5V

4.7µF

1000pF

BAND

SELECT

0V/2V

LDC15D190A0007A

P

GSM

TO

OUT

ANTENNA

35dBm MAX

VCTL

P

3dBm

GSM

IN

7

8

5

1

4

3

49.9Ω

PF08107B

P

DCS

IN

3dBm

VAPC

P

DCS

OUT

2

6

32dBm MAX

500Ω

ATTN

20dB

(OPTIONAL,

SEETEXT)

0.1µF

R1

52.3Ω

AD8315

+V

2.7V

S

1

2

3

4

8

VPOS

VAPC

NC

RFIN

ENBL

VSET

FLTR

ENABLE

0V/2.7V

7

6

5

1

R2

8-BIT

RAMP DAC

0V TO 2.55V

600Ω

1

R3

1kΩ

COMM

150pF

1.5kΩ

NC = NO CONNECT

1

R2, R3 OPTIONAL,

SEE TEXT

Figure 38. Dual-Mode (GSM/DCS) PA Control Example

The operational setpoint voltage, in the range 250 mV to 1.4 V,

is applied to the VSET pin of the AD8315. This is typically

supplied by a DAC. The AD8315’s VAPC output drives the

level control pin of the power amplifier directly. V_APCreaches a

maximum value of approximately 2.5 V on a 2.7 V supply while

delivering the 3 mA required by the level control input of the

PA. This is more than sufficient to exercise the gain control

range of the PA.

MOBILE HANDSET POWER CONTROL EXAMPLE

Figure 38 shows a complete power amplifier control circuit for a

dual-mode handset. The PF08107B (Hitachi), a dual mode

(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata LDC15D190A0007A).

This has a coupling factor of approximately 19 dB for the GSM

band and 14 dB for DCS and an insertion loss of 0.38 dB and

0.45 dB, respectively. Because the PF08107B transmits a maximum

power level of 35 dBm for GSM and 32 dBm for DCS, additional

attenuation of 20 dB is required before the coupled signal is

applied to the AD8315. This results in peak input levels to the

AD8315 of −4 dBm (GSM) and −2 dBm (DCS). While the

AD8315 gives a linear response for input levels up to 2 dBm,

for highly temperature-stable performance at maximum PA

output power, the maximum input level should be limited to

approximately −2 dBm (see Figure 5 and Figure 7). This does,

however, reduce the sensitivity of the circuit at the low end.

During initialization and completion of the transmit sequence,

V_APCshould be held at its minimum level of 250 mV by keeping

V_SETbelow 200 mV.

In this example, V_SETis supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC’s output voltage

can be scaled using two resistors, as shown in Figure 38. This

converts the DAC’s maximum voltage of 2.55 V down to 1.6 V

and increases the control resolution to 0.25 dB/bit.

A filter capacitor (C_FLT) must be used to stabilize the loop. The

choice of C_FLTdepends to a large degree on the gain control

dynamics of the power amplifier, something that is frequently

poorly characterized, so some trial and error can be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kΩ series

resistor is included. This adds a zero to the control loop and

Rev. C | Page 18 of 24

AD8315

increases the phase margin, which helps to make the step response

of the circuit more stable when the PA output power is low and

the slope of the PA’s power control function is the steepest.

In both situations, the voltage on VSET should be kept below

200 mV during power-on and power-off to prevent any

unwanted transients on VAPC.

A smaller filter capacitor can be used by inserting a series

resistor between VAPC and the control input of the PA. A

series resistor works with the input impedance of the PA to

create a resistor divider and reduces the loop gain. The size of

the resistor divider ratio depends upon the available output

swing of V_APCand the required control voltage on the PA.

INPUT COUPLING OPTIONS

The internal 5 pF coupling capacitor of the AD8315, along with

the low frequency input impedance of 2.8 kΩ, give a high-pass

input corner frequency of approximately 16 MHz. This sets the

minimum operating frequency. Figure 40, Figure 41, and Figure 42

show three options for input coupling. A broadband resistive

match can be implemented by connecting a shunt resistor to

ground at RFIN (see Figure 40). This 52.3 Ω resistor (other

values can also be used to select different overall input impedances)

combines with the input impedance of the AD8315 to give a

broadband input impedance of 50 Ω. While the input resistance

and capacitance (C_INand R_IN) of the AD8315 varies from device

to device by approximately 20ꢁ, and over frequency (see

Figure 11), the dominance of the external shunt resistor means

that the variation in the overall input impedance is close to the

tolerance of the external resistor. This method of matching is

most useful in wideband applications or in multiband systems

where there is more than one operating frequency.

This technique can also be used to limit the control voltage in

situations where the PA cannot deliver the power level being

demanded by VAPC. Overdrive of the control input of some

PAs causes increased distortion. It should be noted, however,

that if the control loop opens (that is, V_APCgoes to its maximum

value in an effort to balance the loop), the quiescent current of

the AD8315 increases somewhat, particularly at supply voltages

greater than 3 V.

Figure 39 shows the relationship between V_SETand output

power (P_OUT) at 0.9 GHz . The overall gain control function is

linear in dB for a dynamic range of over 40 dB. Note that for

V_SETvoltages below 300 mV, the output power drops off steeply

as V_APCdrops toward its minimum level of 250 mV.

A reactive match can also be implemented as shown in

Figure 41. This is not recommended at low frequencies as

device tolerances dramatically vary the quality of the match

because of the large input resistance. For low frequencies,

Figure 40 or Figure 42 is recommended.

40

4

+85°C

30

3

+25°C

20

2

+85°C

+25°C

In Figure 41, the matching components are drawn as generic

reactances. Depending on the frequency, the input impedance

and the availability of standard value components, either a

capacitor or an inductor is used. As in the previous case, the

input impedance at a particular frequency is plotted on a Smith

Chart and matching components are chosen (shunt or series L,

shunt or series C) to move the impedance to the center of the chart.

10

1

–30°C

0

–10

–20

–1

–2

–30°C

–3

–4

–30

–40

AD8315

0

0.2

0.4

0.6

0.8

(V)

1.0

1.2

1.4

1.6

V

SET

C

RFIN

Figure 39. P_OUTvs. V_SETat 0.9 GHz for Dual-Mode Handset

Power Amplifier Application, −30°C, +25°C, and +85°C

R

52.3V

SHUNT

C

R

IN

ENABLE AND POWER-ON

The AD8315 can be disabled by pulling the ENBL pin to

ground. This reduces the supply current from its nominal level

of 7.4 mA to 4 μA. The logic threshold for turning on the device

is at 1.5 V with 2.7 V supply voltage. A plot of the enable glitch

is shown in Figure 22. Alternatively, the device can be completely

disabled by pulling the supply voltage to ground. To minimize

glitch in this mode, ENBL and VPOS should be tied together. If

VPOS is applied before the device is enabled, a narrow 750 mV

glitch results (see Figure 29).

Figure 40. Broadband Resistive Input Coupling Option

AD8315

C

X1

RFIN

C

R

IN

X2

IN

Figure 41. Narrow-Band Reactive Input Coupling Option

Rev. C | Page 19 of 24

AD8315

EVALUATION BOARD

ANTENNA

AD8315

Figure 43 shows the schematic of the AD8315 MSOP evaluation

board. The layout and silkscreen of the component side are

shown in Figure 44 and Figure 45. An evaluation board is also

available for the LFCSP package (see the Ordering Guide for

exact part numbers). Apart from the slightly smaller device

footprint, the LFCSP evaluation board is identical to the MSOP

board. The board is powered by a single supply in the 2.7 V to

5.5 V range. The power supply is decoupled by a single 0.1 μF

capacitor.

C

RFIN

STRIPLINE

PA

R

ATTN

C

R

IN

Figure 42. Series Attention Input Coupling Option

Figure 42 shows a third method for coupling the input

signal into the AD8315. A series resistor, connected to the RF

source, combines with the input impedance of the AD8315 to

resistively divide the input signal being applied to the input.

This has the advantage of very little power being tapped off in

RF power transmission applications.

Table 5 details the various configuration options of the

evaluation board.

R2

52.3Ω

C1

0.1µF

TP1

R1

0Ω

AD8315

J1

J2

V

1

8

7

RFIN

VPOS

VAPC

NC

POS

R3

0Ω

USING THE CHIP SCALE PACKAGE

J2

V

POS

2

3

4

VAPC

SW1

ENBL

VSET

On the underside of the chip scale package, there is an exposed

paddle. This paddle is internally connected to the chip’s ground.

There is no thermal requirement to solder the paddle down to

the printed circuit board’s ground plane. However, soldering

down the paddle has been shown to increase the stability over

frequency of the AD8315 ACP’s response at low input power

levels (that is, at around −45 dBm) in the DCS and PCS bands.

R4

(OPEN)

C2

(OPEN)

TP2

6

5

VSET

FLTR COMM

C4

(OPEN)

NC = NO CONNECT

LK2

LK1

V

POS

C3

0.1µF

C5

0.1µF

R8

10kΩ

R7

16.2kΩ

AD8031

R6

17.8kΩ

R5

10kΩ

Figure 43. Evaluation Board Schematic (MSOP)

Table 5. Evaluation Board Configuration Options

Component Function

Default Condition

Not Applicable

SW1 = A

TP1, TP2

SW1

Supply anꢀ Grounꢀ Vector Pins.

Device Enable. When in Position A, the ENdL pin is connecteꢀ to VPOS anꢀ the AD8315 is

in operating moꢀe. In Position d, the ENdL pin is grounꢀeꢀ putting the ꢀevice in power-ꢀown moꢀe.

R1, R2

Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8315’s internal input

impeꢀance to give a broaꢀbanꢀ input impeꢀance of arounꢀ 50 Ω. A reactive match can be

implementeꢀ by replacing R2 with an inꢀuctor anꢀ R1 (0 Ω) with a capacitor. Note that the

AD8315’s RF input is internally ac-coupleꢀ.

R2 = 52.3 Ω (Size 0603)

R1 = 0 Ω (Size 0402)

R3, R4, C2

Output Interface. R4 anꢀ C2 can be useꢀ to check the response of VAPC to capacitive anꢀ resistive

loaꢀing. R3/R4 can be useꢀ to reꢀuce the slope of VAPC.

R4 = C2 = Open (Size 0603)

R3 = 0 Ω (Size 0603)

C1

C4

Power Supply Decoupling. The nominal supply ꢀecoupling consists of a 0.1 μF capacitor.

Filter Capacitor. The response time of VAPC can be moꢀifieꢀ by placing a capacitor between

FLTR (Pin 4) anꢀ grounꢀ.

C1 = 0.1 μF (Size 0603)

C4 = Open (Size 0603)

LK1, LK2

Measurement Moꢀe. A quasimeasurement moꢀe can be implementeꢀ by installing LK1 anꢀ LK2

(connecting an inverteꢀ VAPC to VSET) to yielꢀ the nominal relationship between RFIN anꢀ VSET.

In this moꢀe, a large capacitor (0.01 μF or greater) must be installeꢀ in C4.

LK1, LK2 = Installeꢀ

Rev. C | Page 20 of 24

AD8315

For operation in controller mode, both jumpers, LK1 and LK2,

should be removed. The setpoint voltage is applied to VSET,

RFIN is connected to the RF source (PA output or directional

coupler), and VAPC is connected to the gain control pin of the

PA. When used in controller mode, a capacitor must be installed in

C4 for loop stability. For GSM/DCS handset power amplifiers,

this capacitor should typically range from 150 pF to 300 pF.

A quasimeasurement mode (where the AD8315 delivers an

output voltage that is proportional to the log of the input signal)

can be implemented, to establish the relationship between VSET

and RFIN, by installing the two jumpers, LK1 and LK2. This

mimics an AGC loop. To establish the transfer function of the

log amp, the RF input should be swept while the voltage on

VSET is measured, that is, the SMA connector labeled VSET

now acts as an output. This is the simplest method to validate

operation of the evaluation board. When operated in this mode,

a large capacitor (0.01 μF or greater) must be installed in C4

(filter capacitor) to ensure loop stability.

Figure 44. Layout of Component Side (MSOP)

EVALUATION BOARD REV A

PWUP

AD8315

GND

A

VAPC

J2

TP2

SW1

RFIN

J1

VPOS

TP1

B

R3

PWDN

C1

Z1

R2

R1

C4

J3

R8

A1

R6

LK1

LK2

C3

08 - 006794 REV A

COMPONENT SIDE

VSET

Figure 45. Silkscreen of Component Side (MSOP)

Rev. C | Page 21 of 24

AD8315

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

1

5

4

5.15

4.90

4.65

3.20

3.00

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.00

0.38

0.22

0.23

0.08

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 46. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

1.89

1.74

1.59

3.25

3.00

2.75

0.55

0.40

0.30

0.60

0.45

0.30

5

4

8

2.25

2.00

1.75

BOTTOM VIEW

EXPOSEDPAD

1.95

1.75

1.55

TOP VIEW

0.15

0.10

0.05

1

2.95

2.75

2.55

PIN 1

INDICATOR

0.25

0.20

0.15

0.50 BSC

12° MAX

0.80 MAX

0.65 TYP

1.00

0.85

0.80

0.05 MAX

0.02 NOM

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

Figure 47. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

2 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-1)

Dimensions shown in millimeters

Rev. C | Page 22 of 24

AD8315

ORDERING GUIDE

Model

Temperature Range Package Description

Package Option Ordering Quantity Branding

AD8315ARM

−30°C to +85°C

8-Leaꢀ MSOP, Tube

RM-8

50

J7A

Q0S

AD8315ARM-REEL

AD8315ARM-REEL7

AD8315ARMZ¹

AD8315ARMZ-RL¹

AD8315-EVAL

8-Leaꢀ MSOP, 13" Tape anꢀ Reel

8-Leaꢀ MSOP, 7" Tape anꢀ Reel

8-Leaꢀ MSOP, Tube

8-Leaꢀ MSOP, 13" Tape anꢀ Reel

MSOP Evaluation doarꢀ

3,000

1,000

50

3,000

AD8315ACP-REEL

AD8315ACP-REEL7

AD8315ACPZ-REEL¹

AD8315ACPZ-REEL7¹−30°C to +85°C

AD8315ACP-EVAL

−30°C to +85°C

8-Leaꢀ LFCSP_VD, 13" Tape anꢀ Reel CP-8-1

8-Leaꢀ LFCSP_VD, 7" Tape anꢀ Reel CP-8-1

8-Leaꢀ LFCSP_VD, 13" Tape anꢀ Reel CP-8-1

10,000

3,000

10,000

3,000

J7

0J

8-Leaꢀ LFCSP_VD, 7" Tape anꢀ Reel

LFCSP_VD Evaluation doarꢀ

Die, Surf Tape

CP-8-1

AD8315CSURF

AD8315ACHIPS

DIE

5,000

325

Die, Waffle Pack

¹Z = Pb-free part.

Rev. C | Page 23 of 24

AD8315

NOTES

registered trademarks are the property of their respective owners.

C01520-0-6/06(C)

Rev. C | Page 24 of 24

型号:	AD8315ARMZ
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ANALOG DEVICES INC
零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP8,.19
针数：	8
制造商包装代码：	RM-8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.01
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e3
长度：	3 mm
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-30 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP8,.19
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Other Telecom ICs
最大压摆率：	0.0129 mA
标称供电电压：	2.7 V
表面贴装：	YES
技术：	BIPOLAR
电信集成电路类型：	TELECOM CIRCUIT
温度等级：	OTHER
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	30
宽度：	3 mm
Base Number Matches：	1

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