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3 V, Voltage Monitoring

Microprocessor Supervisory Circuits

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Precision supply voltage monitor

2.63 V (ADM706P, ADM706R, ADM708R)

2.93 V (ADM706S, ADM708S)

3.08 V (ADM706T, ADM708T)

100 μA quiescent current

200 ms reset pulse width

MR

WATCHDOG

INPUT (WDI)

TRANSITION

DETECTOR

WATCHDOG

OUTPUT (WDO)

TIMER

V

RESET AND

WATCHDOG

TIMEBASE

CC

70μA

MR

RESET,

(P = RESET)

RESET

GENERATOR

Debounced manual reset input (

Independent watchdog timer

1.6 second timeout (ADM706x)

Reset output

)

V

CC

V

*

REF

ADM706P/ADM706R/

ADM706S/ADM706T

POWER-FAIL

INPUT (PFI)

POWER-FAIL

Active high (ADM706P)

OUTPUT (PFO)

1.25V

Active low (ADM706R, ADM706S, ADM706T)

Both active high and active low (ADM708R, ADM708S,

ADM708T)

*

VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

Figure 1. ADM706P/ADM706R/ADM706S/ADM706T

Voltage monitor for power-fail or low battery warning

V

CC

RESET

Guaranteed

valid with V_CC= 1 V

70μA

RESET

Superior upgrade for MAX706P/R/S/T, MAX708R/S/T

MR

RESET

GENERATOR

APPLICATIONS

V

CC

Microprocessor systems

Computers

Controllers

V

*

REF

ADM708R/ADM708S/

ADM708T

POWER-FAIL

INPUT (PFI)

POWER-FAIL

OUTPUT (PFO)

1.25V

Intelligent instruments

Critical microprocessor monitoring

Battery-operated systems

Portable instruments

* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)

Figure 2. ADM708R/ADM708S/ADM708T

GENERAL DESCRIPTION

The ADM706P/ADM706R/ADM706S/ADM706T and the

ADM708R/ADM708S/ADM708T microprocessor supervisory

circuits are suitable for monitoring either 3 V or 3.3 V power

supplies.

The ADM706R, ADM706S, and ADM706T are identical except

for the reset threshold monitor levels, which are 2.63 V, 2.93 V, and

3.08 V, respectively. The ADM706P is identical to the ADM706R in

that the reset threshold is 2.63 V. It differs only in that it has an

active high reset output.

The ADM706P/ADM706R/ADM706S/ADM706T provide

power-supply monitoring circuitry that generate a reset output

during power-up, power-down, and brownout conditions. The

reset output remains operational with V_CCas low as 1 V.

Independent watchdog monitoring circuitry is also provided.

This is activated if the watchdog input has not been toggled

within 1.6 seconds.

The ADM708R/ADM708S/ADM708T provide similar functio-

nality as the ADM706R/ADM706S/ADM706T and only differ

in that a watchdog timer function is not available. Instead, an

active high reset output (RESET) is provided in addition to the

RESET

active low ( ) output.

All parts are available in narrow 8-lead PDIP and 8-lead SOIC

packages.

In addition, there is a 1.25 V threshold detector for power-fail

warning, low battery detection, or to monitor an additional power

MR

supply. An active low debounced

input is also included.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 8

Circuit Information........................................................................ 10

Power-Fail Reset ......................................................................... 10

Manual Reset............................................................................... 10

Watchdog Timer (ADM706x) .................................................. 10

Power-Fail Comparator ............................................................. 11

Adding Hysteresis to the Power-Fail Comparator................. 11

RESET

Valid

Below 1 V V_CC..................................................... 11

Applications Information.............................................................. 12

Monitoring Additional Supply Levels...................................... 12

RESET

Microprocessors with Bidirectional

........................... 12

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 14

REVISION HISTORY

5/08—Rev. B to Rev. C

Changes to Applications Section.................................................... 1

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 6

Changes to Figure 8.......................................................................... 7

Changes to Figure 16........................................................................ 9

2/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Table 1............................................................................ 3

Updated Outline Dimensions....................................................... 12

Changes to Ordering Guide .......................................................... 13

Rev. C | Page 2 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

SPECIFICATIONS

V_CC= 2.70 V to 5.5 V (ADM706P/ADM70xR), V_CC= 3.00 V to 5.5 V (ADM70xS), V_CC= 3.15 V to 5.5 V (ADM70xT), T_A= T_MINto T_MAX

unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max Unit Test Conditions/Comments

POWER SUPPLY

V_CCOperating Voltage Range

Supply Current

1.0

5.5

200

350

V

μA

100

150

V_CC< 3.6 V

V_CC< 5.5 V

LOGIC OUTPUT

Reset Threshold (V_RST

)

2.55

2.85

3.00

2.63

2.93

3.08

20

2.70

3.00

3.15

V

mV

ms

ADM706P/ADM70xR

ADM70xS

ADM70xT

Reset Threshold Hysteresis

RESET PULSE WIDTH

160

200

280

ADM706P/ADM70xR, V_CC= 3 V

ADM70xS/ADM70xT, V_CC= 3.3 V

V_CC= 5.0 V

RESET OUTPUT VOLTAGE

(ADM70xR/ADM70xS/ADM70xT)

V_OH

V_OL

V_OH

V_OL

0.8 × V_CC

V

V_RST(max) < V_CC< 3.6 V, I_SOURCE= 500 μA

V_RST(max) < V_CC< 3.6 V, I_SINK= 1.2 mA

4.5 V < V_CC< 5.5 V, I_SOURCE= 800 μA

4.5 V < V_CC< 5.5 V, I_SINK= 3.2 mA

V_CC= 1 V, I_SINK= 100 μA

0.3

V_CC− 1.5 V

0.4

0.3

RESET OUTPUT VOLTAGE (ADM706P)

V_OH

V_OL

V_OH

V_OL

V_CC− 0.6 V

V_CC− 1.5 V

V

V_RST(max) < V_CC< 3.6 V, I_SOURCE= 215 μA

V_RST(max) < V_CC< 3.6 V, I_SINK= 1.2 mA

4.5 V < V_CC< 5.5 V, I_SOURCE= 800 μA

4.5 V < V_CC< 5.5 V, I_SINK= 3.2 mA

0.3

0.4

RESET OUTPUT VOLTAGE (ADM708x)

V_OH

V_OL

V_OH

V_OL

0.8 × V_CC

V

V_RST(max) < V_CC< 3.6 V, I_SOURCE= 500 μA

V_RST(max) < V_CC< 3.6 V, I_SINK= 500 μA

4.5 V < V_CC< 5.5 V, I_SOURCE= 800 μA

4.5 V < V_CC< 5.5 V, I_SINK= 1.2 mA

0.3

0.4

V_CC− 1.5 V

WATCHDOG INPUT (ADM706x)

Watchdog Timeout Period

1.00

1.60

2.25 sec

ADM706P/ADM706R: V_CC= 3 V;

ADM706S/ADM706T: V_CC= 3.3 V;

V_IL= 0.4 V, V_IH= V_CC× 0.8 V

WDI Pulse Width

100

50

ns

V_RST(max) < V_CC< 3.6 V

4.5 V < V_CC< 5.5 V

WDI Input Threshold

V_IL

V_IH

V_IL

V_IH

0.6

0.8

V

V_RST(max) < V_CC< 3.6 V

V_CC= 5.0 V

0.7 × V_CC

3.5

V_CC= 5.0 V

WDI Input Current

WDO OUTPUT VOLTAGE

V_OH

−1.0

+0.02 +1.0 μA

WDI = 0 V or V_CC

0.8 × V_CC

V_CC− 1.5 V

V

V_RST(max) < V_CC< 3.6 V, I_SOURCE= 500 μA

4.5 V < V_CC< 5.5 V, I_SOURCE= 800 μA

V_RST(max) < V_CC< 3.6 V, I_SINK= 500 μA

4.5 V < V_CC< 5.5 V, I_SINK= 1.2 mA

V_OL

0.3

0.4

V

Rev. C | Page 3 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

Parameter

Min

Typ

Max Unit Test Conditions/Comments

MANUAL RESET INPUT

MR Pull-Up Current (MR = 0 V)

25

70

250

600

μA

ns

V

_RST(max) < V_CC< 3.6 V

4.5 V < V_CC< 5.5 V

_RST(max) < V_CC< 3.6 V

100

500

150

250

MR Pulse Width

V

ns

4.5 V < V_CC< 5.5 V

MR INPUT THRESHOLD

V_IL

V_IH

V_IL

V_IH

0.6

0.8

V

V_RST(max) < V_CC< 3.6 V

4.5 V < V_CC< 5.5 V

0.7 × V_CC

2.0

4.5 V < V_CC< 5.5 V

MR TO RESET OUTPUT DELAY

750

250

ns

V_RST(max) < V_CC< 3.6 V

4.5 V < V_CC< 5.5 V

POWER-FAIL INPUT

PFI Input Threshold

1.2

1.25

1.3

V

ADM70xP/ADM70xR, V_CC= 3 V

ADM70xS/ADM70xT, V_CC= 3.3 V, PFI falling

PFI Input Current

−25

+0.01 +25 nA

PFO OUTPUT VOLTAGE

V_OH

V_OL

V_OH

V_OL

0.8 × V_CC

V

V_RST(max) < V_CC< 3.6 V, I_SOURCE= 500 μA

V_RST(max) < V_CC< 3.6 V, I_SINK= 1.2 mA

4.5 V < V_CC< 5.5 V, I_SOURCE= 800 μA

4.5 V < V_CC< 5.5 V, I_SINK= 3.2 mA

0.3

0.4

V

V_CC− 1.5 V

Rev. C | Page 4 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 2.

Parameter

Rating

V_CC

−0.3 V to +6 V

−0.3 V to V_CC+ 0.3 V

All Other Inputs

Input Current

V_CC

GND

20 mA

ESD CAUTION

Digital Output Current

Power Dissipation, N-8 (PDIP)

θ_JAThermal Impedance

Power Dissipation, R-8 (SOIC)

θ_JAThermal Impedance

Operating Temperature Range

Industrial (Version A)

Lead Temperature (Soldering, 10 sec)

Vapor Phase (60 sec)

Infrared (15 sec)

20 mA

727 mW

135°C/W

470 mW

110°C/W

−40°C to +85°C

300°C

215°C

220°C

Storage Temperature Range

ESD Rating

−65°C to +150°C

>4.5 kV

Rev. C | Page 5 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

MR

1

2

3

4

8

7

6

5

WDO

RESET

WDI

MR

1

2

3

4

8

7

6

5

WDO

ADM706R/

ADM706S/

V

ADM706P

V

RESET

CC

ADM706T

TOP VIEW

(Not to Scale)

GND

WDI

PFO

TOP VIEW

(Not to Scale)

PFI

PFO

Figure 3. ADM706P

Figure 4. ADM706R/ADM706S/ADM706T

Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T

Pin No.

Mnemonic Description

1

MR

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven

from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An

internal 70 μA pull-up current holds the input high when floating.

2

3

4

V_CC

GND

PFI

Power Supply Input.

Ground. Ground reference for all signals (0 V).

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less

than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.

5

6

PFO

WDI

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is

less than 1.25 V.

Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout

period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI

input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is

also cleared whenever reset is asserted.

7 (ADM706R/ADM706S/

ADM706T Only)

RESET

Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V_CCbeing

below the reset threshold or by a low signal on the MR input. RESET remains low whenever V_CC

is below the reset threshold. It remains low for 200 ms after V_CCgoes above the reset threshold

or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is

connected to MR.

7 (ADM706P Only)

8

RESET

WDO

Logic Output. RESET is an active high output suitable for systems that use active high reset

logic. It is the inverse of RESET.

Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of

inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes

low during low line conditions. Whenever V_CCis below the reset threshold, WDO remains low. As

soon as V_CCgoes above the reset threshold, WDO goes high immediately.

Rev. C | Page 6 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

MR

1

2

3

4

8

7

6

5

RESET

NC

ADM708R/

ADM708S/

ADM708T

TOP VIEW

V

CC

GND

PFI

PFO

(Not to Scale)

NC = NO CONNECT

Figure 5. ADM708R/ADM708S/ADM708T

Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T

Pin No.

Mnemonic Description

1

MR

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS

logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds

the input high when floating.

2

3

4

V_CC

GND

PFI

Power Supply Input.

Ground. Ground reference for all signals (0 V).

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO

goes low. If unused, PFI should be connected to GND.

5

6

7

PFO

NC

RESET

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V.

No Connect.

Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V_CCbeing below the reset

threshold or by a low signal on the MR input. RESET remains low whenever V_CCis below the reset threshold. It

remains low for 200 ms after V_CCgoes above the reset threshold or MR goes from low to high. A watchdog

timeout does not trigger RESET unless WDO is connected to MR.

8

RESET

Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the

inverse of RESET.

Rev. C | Page 7 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 3.3V

CC

= 25°C

T

A

1.3V

PFI

1.2V

PFO

0V

V

CC

3V

RESET

400ms/DIV

500ns/DIV

Figure 6. ADM70xR/ADM70xS/ADM70xT

Figure 9. PFI Deassertion Response Time

RESET

Output Voltage vs. Supply Voltage

V

= V

RT

CC

= 25°C

T

A

3V

V

RESET

CC

RESET

0V

400ms/DIV

100ns/DIV

Figure 7. RESET Output Voltage vs. Supply Voltage

RESET

Figure 10.

, RESET Assertion

V

= 3.3V

V

= V

RT

CC

= 25°C

CC

T = 25°C

A

T

A

1.3V

PFI

3V

0V

3V

0V

1.2V

PFO

0V

RESET

3V

500ns/DIV

100ns/DIV

Figure 8. PFI Assertion Response Time

RESET

, RESET Deassertion

Figure 11.

Rev. C | Page 8 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

T

= 25°C

A

3V

CC

V

2V

3V

RESET

0V

2µs/DIV

RESET

Figure 12. ADM70xR/ADM70xS/ADM70xT

Response Time

Rev. C | Page 9 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

CIRCUIT INFORMATION

MANUAL RESET

WATCHDOG

INPUT (WDI)

WATCHDOG

TIMER

MR

The

input allows other reset sources, such as a manual reset

TRANSITION

WATCHDOG

OUTPUT (WDO)

DETECTOR

switch, to generate a processor reset. The input is effectively

V

MR

RESET AND

WATCHDOG

TIMEBASE

debounced by the timeout period (200 ms typical). The

CC

input is TTL-/CMOS-compatible; it can also be driven by any

70μA

MR

logic reset output. If unused, the

left floating.

input can be tied high or

MR

RESET,

(P = RESET)

RESET

GENERATOR

V

CC

V

RT

V

*

RT

CC

REF

ADM706P/ADM706R/

ADM706S/ADM706T

POWER-FAIL

INPUT (PFI)

t_RS

POWER-FAIL

OUTPUT (PFO)

1.25V

RESET

MR

*

VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

Figure 13. ADM706 Functional Block Diagram

MR EXTERNALLY

DRIVEN LOW

V

CC

WDO

70μA

RESET

MR

NOTES

RESET = COMPLEMENT OF RESET

RESET

GENERATOR

V

CC

RESET MR

WDO

Timing

Figure 15.

,

, and

V

*

REF

ADM708R/ADM708S/

ADM708T

POWER-FAIL

INPUT (PFI)

WATCHDOG TIMER (ADM706x)

POWER-FAIL

OUTPUT (PFO)

1.25V

The watchdog timer circuit is used to monitor the activity of the

microprocessor to check that it is not stalled in an indefinite loop.

An output line on the processor is used to toggle the watchdog

input (WDI) line. If this line is not toggled within the timeout

* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)

Figure 14. ADM708 Functional Block Diagram

POWER-FAIL RESET

WDO

period (1.6 seconds), the watchdog output ( ) is driven low.

RESET

The reset output provides a reset (RESET or

) output

WDO

output is connected to a nonmaskable interrupt (NMI)

The

signal to the microprocessor whenever the V_CCinput is below

the reset threshold. The actual reset threshold voltage is dependent

on whether a P, R, S, or T suffix device is used. An internal timer

holds the reset output active for 200 ms after the voltage on V_CC

rises above the threshold. This is intended as a power-on reset

signal for the microprocessor. It allows time for both the power

supply and the microprocessor to stabilize after power-up. If a

power supply brownout or interruption occurs, the reset line is

similarly activated and remains active for 200 ms after the supply

recovers. If another interruption occurs during an active reset

period, the reset timeout period continues for an additional 200 ms.

on the processor. Therefore, if the watchdog timer times out, an

interrupt is generated. The interrupt service routine is used to

rectify the problem.

The watchdog timer is cleared either by a high-to-low or by a

low-to-high transition on WDI. Pulses as narrow as 50 ns are

RESET

detected. The timer is also cleared by RESET/

going

active. Therefore, the watchdog timeout period begins after

reset goes inactive.

WDO

When V_CCfalls below the reset threshold,

is forced low

whether or not the watchdog timer has timed out. Normally,

RESET

The reset output is guaranteed to remain valid with V_CCas low

as 1 V. This ensures that the microprocessor is held in a stable

shutdown condition as the power supply starts up.

this generates an interrupt, but it is overridden by RESET/

going active.

t_WP

t_WD

WDI

The ADM706P provides an active high RESET signal; the

RESET

ADM706R/ADM706S/ADM706T provide an active low

signal; and the ADM708R/ADM706S/ADM706T provide both

RESET

WDO

RESET and

.

RESET EXTERNALLY

TRIGGERED BY MR

RESET

t_RS

Figure 16. Watchdog Timing

Rev. C | Page 10 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

3.3V

POWER-FAIL COMPARATOR

INPUT

POWER

ADM663A

The power-fail comparator is an independent comparator that

can be used to monitor the input power supply. The inverting

input of the comparator is internally connected to a 1.25 V

reference voltage. The noninverting input is available at the PFI

input. This input is used to monitor the input power supply via

a resistive divider network. When the voltage on the PFI input

V

CC

R1

TO MICROPROCESSOR NMI

1.25V

–

PFO

+

PFI

R2

ADM706P/ADM706R/

ADM706S/ADM706T/

ADM708R/ADM708S/

ADM708T

PFO

drops below 1.25 V, the comparator output (

) goes low,

R3

indicating a power failure. For early warning of power failure,

the comparator is used to monitor the preregulator input simply

3.3V

PFO

by choosing an appropriate resistive divider network. The

output is used to interrupt the processor so that a shutdown

procedure is implemented before the power is lost.

INPUT

POWER

0V

V

H

V

L

1.25V

V

R1

R2

PFO

IN

POWER-FAIL

OUTPUT

Figure 18. Adding Hysteresis to the Power-Fail Comparator

POWER-FAIL PFI

INPUT

ADM706P/ADM706R/

ADM706S/ADM706T/

ADM708R/ADM708S/

ADM708T

⎡

⎤

⎛

⎜

⎝

⎞

⎟

⎠

R2 + R3

R2 × R3

V_H= 1.25 ⎢1 +

R1⎥

⎢

⎣

⎥

⎦

V_CC− 1.25

1.25

R2

⎛

⎜

⎞

⎟

V = 1.25 + R1

−

L

R3

Figure 17. Power-Fail Comparator

⎝

⎠

R1 + R2

R2

⎛

⎜

⎞

⎟

ADDING HYSTERESIS TO THE POWER-FAIL

COMPARATOR

V_MID= 1.25

⎝

⎠

For increased noise immunity, hysteresis can be added to the

power-fail comparator. Because the comparator circuit is

noninverting, hysteresis is added simply by connecting a resistor

VALID RESET BELOW 1 V V_CC

The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/

ADM708T are guaranteed to provide a valid reset level with V_CC

as low as 1 V. Refer to the Typical Performance Characteristics

section. As V_CCdrops below 1 V, the internal transistor does not

have sufficient drive to hold it on so the voltage on

longer held at 0 V. A pull-down resistor, as shown in Figure 19, can

be connected externally to hold the line low if it is required.

PFO

between the

output and the PFI input as shown in Figure 18.

is low, Resistor R3 sinks current from the summing

PFO

When

junction at the PFI pin. When

is high, Resistor R3 sources

RESET

is no

current into the PFI summing junction. This results in differing

trip levels for the comparator. Further noise immunity is achieved

by connecting a capacitor between PFI and GND.

ADM706R/ADM706S/

ADM706T/ADM708R/

ADM708S/ADM708T

RESET

GND

R1

RESET

Figure 19.

Valid Below 1 V

Rev. C | Page 11 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

APPLICATIONS INFORMATION

A typical operating circuit is shown in Figure 20. The unregulated

dc input supply is monitored using the PFI input via the resistive

divider network. Resistor R1 and Resistor R2 are to be selected

so that when the supply voltage drops below the desired level

(for example, 5 V), the voltage on PFI drops below the 1.25 V

threshold, thereby generating an interrupt to the microprocessor.

Monitoring the preregulator input gives additional time to

execute an orderly shutdown procedure before power is lost.

MONITORING ADDITIONAL SUPPLY LEVELS

It is possible to use the power-fail comparator to monitor a second

supply as shown in Figure 22. The two sensing resistors, R1 and

R2, are selected such that the voltage on PFI drops below 1.25 V at

PFO

the minimum acceptable input supply. The

output can be

MR

connected to the

input so that a reset is generated when

the supply drops out of tolerance. In this case, if either supply

drops out of tolerance, a reset is generated.

UNREGULATED

ADM666A

V

+3V/+3.3V

DC

X

IN

OUT

3.3V

GND

V

CC

RESET

R1

R2

V

CC

MICROPROCESSOR

WDI

PFO

ADM706R/

ADM706S/

ADM706T

RESET

WDI

I/O LINE

PFI

MR

ADM706R/

ADM706S/

ADM706T

MICROPROCESSOR

NMI

GND

PFI

MR

WDO

PFO

INTERRUPT

GND

Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, V_X

GND

MANUAL

RESET

MICROPROCESSORS WITH BIDIRECTIONAL RESET

To prevent contention for microprocessors with a bidirectional

reset line, a current limiting resistor is to be inserted between

the ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/

Figure 20. Typical Application Circuit

Microprocessor activity is monitored using the WDI input. This

is driven using an output line from the processor. The software

routines toggle this line at least once every 1.6 seconds. If a problem

RESET

ADM708T

output pin and the microprocessor reset pin.

This limits the current to a safe level if there are conflicting output

reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is

required for other uses, it should be buffered as shown in Figure 23.

WDO

occurs and this line is not toggled,

goes low and a nonmask-

able interrupt is generated. This interrupt routine is to be used

to clear the problem.

BUFFERED

+3V/+3.3V

RESET

If, in the event of inactivity on the WDI line, a system reset is

V

CC

WDO

required, the

shown in Figure 21.

output is to be connected to the input as

ADM706R/ADM706S/

ADM706T/ADM708R/

ADM708S/ADM708T

MICROPROCESSOR

RESET

GND

ADM706R/

ADM706S/

ADM706T

I/O LINE

WDI

PFI

MR

RESET

Figure 23. Bidirectional Input/Output

MICROPROCESSOR

WDO

GND

RESET

Figure 21.

from WDO

Rev. C | Page 12 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

1

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-8)

Dimension shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Rev. C | Page 13 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

ORDERING GUIDE

Model

ADM706PAN

ADM706PANZ¹

Temperature Range

−40°C to +85°C

Package Description

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

Package Option

N-8

R-8

ADM706PAR

ADM706PAR-REEL

ADM706PARZ¹

ADM706PARZ-REEL¹

ADM706RAN

ADM706RANZ¹

ADM706RAR

ADM706RAR-REEL

ADM706RAR-REEL7

ADM706RARZ¹

ADM706RARZ-REEL¹

ADM706RARZ-REEL7¹

ADM706SAN

ADM706SANZ¹

ADM706SAR

ADM706SAR-REEL

ADM706SARZ¹

ADM706SARZ-REEL¹

ADM706TAN

ADM706TANZ¹

ADM706TAR

ADM706TAR-REEL

ADM706TARZ¹

ADM706TARZ-REEL¹

ADM708RAN

ADM708RANZ¹

ADM708RAR

ADM708RAR-REEL

ADM708RARZ¹

ADM708RARZ-REEL¹

ADM708SAN

ADM708SANZ¹

ADM708SAR

ADM708SAR-REEL

ADM708SARZ¹

ADM708SARZ-REEL¹

ADM708TAN

ADM708TANZ¹

ADM708TAR

ADM708TAR-REEL

ADM708TARZ¹

ADM708TARZ-REEL¹

R-8

N-8

R-8

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

R-8

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

R-8

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

R-8

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

R-8

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

R-8

¹Z = RoHS Compliant Part.

Rev. C | Page 14 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

NOTES

Rev. C | Page 15 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

NOTES

registered trademarks are the property of their respective owners.

D06435-0-5/08(C)

Rev. C | Page 16 of 16

型号:	ADM706TARZ-REEL
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	ROCHESTER ELECTRONICS LLC
零件包装代码：	SOIC
包装说明：	ROHS COMPLIANT, MS-012AA, SOIC-8
针数：	8
Reach Compliance Code：	unknown
风险等级：	5.15
Is Samacsys：	N
其他特性：	RESET THRESHOLD VOLTAGE IS 3.08V; MANUAL RESET INPUT
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3
长度：	4.9 mm
湿度敏感等级：	1
信道数量：	1
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	3.15 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	MATTE TIN
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm
Base Number Matches：	1

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