ADV7619KSVZ应用文章市场行情现货热卖使用介绍供应商报价-中国IC网-芯三七

Dual Port, Xpressview,

3 GHz HDMI Receiver

ADV7619

Data Sheet

Advanced audio mute feature

FEATURES

Dedicated, flexible audio output port

Super Audio CD® (SACD) with DSD output interface

HBR audio

Dolby® TrueHD

DTS-HD Master Audio™

High-Definition Multimedia Interface (HDMI®) 1.4a features

supported

All mandatory and additional 3D video formats supported

Extended colorimetry, including sYCC601, Adobe® RGB,

Adobe YCC601, xvYCC extended gamut color

CEC 1.4-compatible

HDMI 3 GHz receiver

297 MHz maximum TMDS clock frequency

Supports 4k × 2k resolution

Xpressview fast switching of HDMI ports

Up to 48-bit Deep Color with 36-/30-/24-bit support

High-bandwidth Digital Content Protection (HDCP) 1.4

support with internal HDCP keys

HDCP repeater support: up to 127 KSVs supported

Integrated CEC controller

General

Interrupt controller with 2 interrupt outputs

Standard identification (STDI) circuit

Highly flexible, 48-bit pixel output interface

36-bit output for resolutions up to 1080p Deep Color

2 × 24-bit pass-through outputs for HDMI formats

greater than 2.25 GHz

Internal EDID RAM

Any-to-any, 3 × 3 color space conversion (CSC) matrix

128-lead TQFP_EP, 14 mm × 14 mm package

Programmable HDMI equalizer

5 V detect and Hot Plug assert for each HDMI port

Audio support

Audio support including high bit rate (HBR) and

Direct Stream Digital (DSD)

S/PDIF (IEC 60958-compatible) digital audio support

Supports up to four I²S outputs

APPLICATIONS

Projectors

Video conferencing

HDTV

AVR, HTiB

Soundbar

Video switch

FUNCTIONAL BLOCK DIAGRAM

ADV7619

FAST

SWITCH

48

HS

VS/FIELD

DE

HDCP

KEYS

HS/VS

FIELD/DE

CLK

36

COMPONENT

PROCESSOR

CLK

TMDS

HDMI1

36-/48-BIT

OUTPUT BUS

DDC

DATA

DEEP

COLOR

HDMI Rx

2

I S

TMDS

HDMI2

S/PDIF

DSD

AUDIO

OUTPUT

DDC

HBR

MCLK

SCLK

MCLK

SCLK

LRCLK

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADV7619

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Supply Recommendations................................................. 13

Power-Up Sequence ................................................................... 13

Power-Down Sequence.............................................................. 13

Current Rating Requirements for Power Supply Design...... 13

Functional Overview...................................................................... 14

HDMI Receiver........................................................................... 14

Component Processor (CP)...................................................... 14

Other Features ............................................................................ 14

Pixel Input/Output Formatting .................................................... 15

Pixel Data Output Mode Features............................................ 15

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Detailed Functional Block Diagram .......................................... 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Data and I²C Timing Characteristics......................................... 6

Absolute Maximum Ratings............................................................ 8

Package Thermal Performance................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

REVISION HISTORY

5/12—Rev. A to Rev. B

9/11—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to General Description Section and Figure 2 ............... 3

Change to Table 1 ............................................................................. 4

Changes to Table 3............................................................................ 6

Changes to Figure 5; Deleted Figure 6, Renumbered

Sequentially ....................................................................................... 7

Changes to Figure 7.......................................................................... 9

Changes to Table 5 .......................................................................... 11

Changes to HDMI Receiver Section and Other Features

Changes to General Description Section ......................................3

Changes to Data Output Transition Time Typ Values, Table 3...6

Changes to Pin 113 Description................................................... 12

Changes to Pixel Input/Output Formatting Section.................. 16

Added Endnote 1 to Table 7 .......................................................... 17

Added Endnote 1 to Table 12 ........................................................ 22

Changes to Ordering Guide.......................................................... 23

7/11—Revision 0: Initial Version

Section.............................................................................................. 14

Deleted Time-Division Multiplexed (TDM) Mode Section

and Figure 9..................................................................................... 15

Rev. B | Page 2 of 24

Data Sheet

ADV7619

GENERAL DESCRIPTION

The ADV7619 is a high quality, two input, one output (2:1)

multiplexed High-Definition Multimedia Interface (HDMI®)

receiver. The ADV7619 is offered in professional (no HDCP

keys) and commercial versions. The operating temperature

range is 0°C to 70°C.

The HDMI receiver has advanced audio functionality, such as

a mute controller, that prevents audible extraneous noise in the

audio output.

The ADV7619 contains one main component processor (CP),

which processes video signals from the HDMI receiver up to

1080p 36-bit Deep Color. It provides features such as contrast,

brightness and saturation adjustments, STDI detection block,

free-run, and synchronization alignment controls.

The ADV7619 incorporates a dual input HDMI-capable

receiver that supports all mandatory 3D TV formats defined in

the HDMI 1.4a specification, HDTV formats up to 1080p 36-bit

Deep Color/2160p 8-bit, and display resolutions up to 4k × 2k

(3840 × 2160 at 30 Hz). It integrates an HDMI CEC controller

that supports the capability discovery and control (CDC) feature.

For video formats with pixel clocks higher than 170 MHz, the

video signals received on the HDMI receiver are output directly

to the pixel port output. To accommodate the higher bandwidth

required for these higher resolutions, the output on the pixel bus

consists of two 24-bit buses running at up to 150 MHz: one bus

contains the even pixels, and the other bus contains the odd

pixels. When these two buses are combined, they allow the

transfer of video data with pixel clocks up to 300 MHz. In this

mode, both 4:4:4 RGB 8-bit and 4:2:2 12-bit are supported.

The ADV7619 incorporates Xpressview™ fast switching on both

input HDMI ports. Using the Analog Devices, Inc., hardware-

based HDCP engine to minimize software overhead, Xpressview

technology allows fast switching between both HDMI input ports

in less than 1 sec.

Each HDMI port has dedicated 5 V detect and Hot Plug™ assert

pins. The HDMI receiver also includes an integrated program-

mable equalizer that ensures robust operation of the interface

with long cables.

Fabricated in an advanced CMOS process, the ADV7619

is provided in a 14 mm × 14 mm, 128-lead, surface-mount,

RoHS-compliant TQFP_EP package and is specified over the

0°C to 70°C temperature range.

The ADV7619 offers a flexible audio output port for audio data

extraction from the HDMI stream. HDMI audio formats, includ-

ing SACD via DSD and HBR, are supported by the ADV7619.

DETAILED FUNCTIONAL BLOCK DIAGRAM

XTALP

XTALN

DPLL

P0 TO P11

P12 TO P23

P24 TO P35

P36 TO P47

LLC

300MHz VIDEO PATH

SCL

SDA

CS

CONTROL

INTERFACE

2

I C

CEC

CONTROLLER

HS

BACK-END

COLOR

SPACE

CEC

VS/FIELD/ALSB

DE

RXA_5V

RXB_5V

HPA_A/INT2*

HPA_B

5V DETECT

AND HDP

CONTROLLER

CONTROL AND DATA

CONVERSION

INTERRUPT

CONTROLLER

(INT1, INT2)

INT1

DDCA_SDA

DDCA_SCL

DDCB_SDA

DDCB_SCL

EDID

REPEATER

CONTROLLER

HDMI

PROCESSOR

INT2*

HDCP

KEYS

COMPONENT

PROCESSOR

AP1

AP2

AP3

AP4

A

B

C

DATA

PREPROCESSOR

AND COLOR

SPACE

RXA_C±

RXB_C±

HDCP

ENGINE

PLLs

CONVERSION

AP5

PACKET/

RXA_0±

RXA_1±

RXA_2±

SCLK/INT2*

INFOFRAME

MEMORY

EQUALIZER

SAMPLER

MUTE

PACKET

PROCESSOR

MCLK/INT2*

AP0

AUDIO

PROCESSOR

RXB_0±

RXB_1±

RXB_2±

ADV7619

*INT2 CAN BE MADE AVAILABLE ON ONE OF THESE PINS: HPA_A/INT2, MCLK/INT2, OR SCLK/INT2.

Figure 2.

Rev. B | Page 3 of 24

ADV7619

Data Sheet

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,

operating temperature range, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IH

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL INPUTS¹

Input High Voltage

XTALN and XTALP pins

Other digital inputs

XTALN and XTALP pins

Other digital inputs

RESET and CS pins

1.2

2

V

µA

pF

Input Low Voltage

Input Current

V_IL

0.4

0.8

±±0

I_IN

±45

±10

Other digital inputs

Input Capacitance

C_IN

10

DIGITAL INPUTS (5 V TOLERANT)¹

DDCA_SCL, DDCA_SDA,

DDCB_SCL, and DDCB_SDA pins

Input High Voltage

Input Low Voltage

Input Current

V_IH

V_IL

I_IN

2.±

V

µA

0.8

+70

−70

2.4

DIGITAL OUTPUTS¹

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

V_OH

V_OL

I_LEAK

V

µA

pF

0.4

±±0

±70

VS/FIELD/ALSB pin

HPA_A/INT2 and HPA_B pins

Other digital outputs

±35

±10

Output Capacitance

POWER REQUIREMENTS

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Terminator Power Supply

Comparator Power Supply

CURRENT CONSUMPTION

Digital Core Power Supply

C_OUT

20

DVDD

DVDDIO

PVDD

TVDD

CVDD

1.71

3.14

1.71

3.14

1.71

1.8

3.3

1.8

3.3

1.8

1.89

3.4±

1.89

3.4±

1.89

V

See Table 2

I_DVDD

I_DVDDIO

I_PVDD

I_TVDD

I_CVDD

Test Condition 1

Test Condition 2

Test Condition 1

Test Condition 2

Test Condition 1

Test Condition 2

Test Condition 1

Test Condition 2

Test Condition 1

Test Condition 2

See Table 2, Test Condition 3

2±8

18±

9

10

20

31

92

187

1±±

mA

Digital I/O Power Supply

PLL Power Supply

Terminator Power Supply

Comparator Power Supply

POWER-DOWN CURRENT²

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Terminator Power Supply

Comparator Power Supply

POWER-UP TIME

I_{DVDD_PD}

I_{DVDDIO_PD}

I_{PVDD_PD}

I_{TVDD_PD}

I_{CVDD_PD}

t_PWRUP

1.07

mA

ms

0.034

0.±91

0.857

0.053

25

¹Data guaranteed by characterization.

²Data recorded during lab characterization.

Rev. B | Page 4 of 24

Data Sheet

ADV7619

Table 2. Test Conditions for Current Requirements

Parameter

Value Used

TEST CONDITION 1

Number of HDMI Inputs (Xpressview Mode)

Xpressview

Two inputs

On

Video Format (Each HDMI Input)

HDCP Decryption

4k × 2k

Off

Video Pattern (Each HDMI Input)

Temperature

SMPTE

20°C

Power Supply Voltages

Nominal

TEST CONDITION 2

Number of HDMI Inputs (Xpressview Mode)

Xpressview

Two inputs

On

Video Format (Each HDMI Input)

HDCP Decryption

1080p±0, 3± bits

Off

Video Pattern (Each HDMI Input)

Temperature

SMPTE

20°C

Power Supply Voltages

Nominal

TEST CONDITION 3 (POWER-DOWN)

Number of HDMI Inputs (Xpressview Mode)

Xpressview

N/A

Video Format (Each HDMI Input)

HDCP Decryption

N/A

Video Pattern (Each HDMI Input)

Temperature

N/A

20°C

Power Supply Voltages

Nominal

Other Test Parameters

Power-Down Mode 0 (IO map, Register 0x0C = 0x±2)

Ring oscillator powered down (HDMI map, Register 0x48 = 0x01)

DDC pads powered off (HDMI map, Register 0x73 = 0x03)¹

¹For information about these registers, see the Hardware User Guide for the ADV7±19 (UG-237).

Rev. B | Page 5 of 24

ADV7619

Data Sheet

DATA AND I²C TIMING CHARACTERISTICS

Table 3.

Parameter

Symbol Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal Frequency, XTAL

Crystal Frequency Stability

LLC Frequency Range

I²C PORTS

28.63636

MHz

ppm

MHz

±±5

175

13.±

SCL Frequency

455

kHz

ns

μs

ns

μs

SCL Minimum Pulse Width High¹

SCL Minimum Pulse Width Low¹

Start Condition Hold Time¹

Start Condition Setup Time¹

SDA Setup Time¹

t₁

t₂

t₃

t₄

t_±

t₆

t₇

t₈

655

1.3

655

155

SCL and SDA Rise Time¹

SCL and SDA Fall Time¹

Stop Condition Setup Time¹

RESET FEATURE

355

5.6

±

Reset Pulse Width

ms

CLOCK OUTPUTS

LLC Mark-Space Ratio¹

DATA AND CONTROL OUTPUTS^{1, 2}

Data Output Transition Time

t₉:t₁₅

4±:±±

±±:4±

% duty cycle

t₁₁

t₁₂

End of valid data to negative LLC edge

Negative LLC edge to start of valid data

1.5

5.1

ns

I²S PORT, MASTER MODE¹

SCLK Mark-Space Ratio

LRCLK Data Transition Time

t_1±:t₁₆

t₁₇

t₁₈

t₁₉

t₂₅

4±:±±

±±:4±

15

±

% duty cycle

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

ns

I2Sx Data Transition Time

±

¹Data guaranteed by characterization.

²DLL bypassed on clock path.

Timing Diagrams

t₃

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

Rev. B | Page 6 of 24

Data Sheet

ADV7619

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P47, HS,

VS/FIELD/ALSB, DE

Figure 4. Pixel Port and Control SDR Output Timing

t₁₅

SCLK

t₁₆

t₁₇

LRCLK

I2Sx

t₁₈

t₁₉

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t₂₀

t₁₉

I2Sx

2

MSB

I S MODE

MSB – 1

t₂₀

t₁₉

I2Sx

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₂₀

NOTES

1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN.

2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE

ON THE FOLLOWING PINS: AP1, AP2, AP3, AND AP4.

Figure 5. I²S Timing

Rev. B | Page 7 of 24

ADV7619

Data Sheet

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL PERFORMANCE

Table 4.

To reduce power consumption when using the ADV7619, the

user is advised to turn off the unused sections of the part.

Parameter

Rating

DVDD to GND

PVDD to GND

DVDDIO to GND

CVDD to GND

TVDD to GND

Digital Inputs to GND

2.2 V

4.0 V

2.2 V

Due to PCB metal variation and, therefore, variation in PCB

heat conductivity, the value of θ_JAmay differ for various PCBs.

The most efficient measurement solution is obtained using the

package surface temperature to estimate the die temperature

because this solution eliminates the variance associated with

the θ_JAvalue.

4.0 V

GND − 0.3 V to DVDDIO + 0.3 V

5.3 V

5 V Tolerant Digital Inputs

to GND¹

Digital Outputs to GND

XTALP, XTALN

SCL, SDA Data Pins to

DVDDIO

GND − 0.3 V to DVDDIO + 0.3 V

−0.3 V to PVDD + 0.3 V

DVDDIO − 0.3 V to DVDDIO + 3.± V

The maximum junction temperature (T_{J MAX}) of 125°C must not

be exceeded. The following equation calculates the junction

temperature using the measured package surface temperature

and applies only when no heat sink is used on the device under

test (DUT):

Maximum Junction

Temperature (T_{J MAX}

125°C

)

T_J= T_S+ (Ψ_JT× W_TOTAL

where:

T_Sis the package surface temperature (°C).

_JT= 0.22°C/W for the 128-lead TQFP_EP.

_TOTAL= ((PVDD × I_PVDD) + (0.2 × TVDD × I_TVDD) +

)

Storage Temperature Range −±0°C to +150°C

Infrared Reflow Soldering

(20 sec)

2±0°

Ψ

¹The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,

DDCA_SDA, DDCB_SCL, and DDCB_SDA.

W

(CVDD × I_CVDD) + (DVDD × I_DVDD) + (DVDDIO × I_DVDDIO))

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

where 0.2 is 20% of the TVDD power that is dissipated on the

part itself.

ESD CAUTION

Rev. B | Page 8 of 24

Data Sheet

ADV7619

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

GND

CVDD

NC

PIN 1

VS/FIELD/ALSB

HS

RXA_C–

RXA_C+

TVDD

DE

5

DVDDIO

P0

6

RXA_0–

RXA_0+

TVDD

7

P1

8

P2

9

P3

RXA_1–

RXA_1+

TVDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P4

P5

RXA_2–

RXA_2+

CVDD

P6

P7

P8

GND

P9

ADV7619

TOP VIEW

(Not to Scale)

TEST1

DVDD

P10

P11

TEST2

CVDD

DVDD

P12

RXB_C–

RXB_C+

TVDD

DVDDIO

P13

P14

RXB_0–

RXB_0+

TVDD

P15

P16

P17

RXB_1–

RXB_1+

TVDD

P18

P19

P20

RXB_2–

RXB_2+

CVDD

P21

P22

P23

GND

DVDDIO

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE EXPOSED PAD (PIN 0) ON THE BOTTOM

OF THE PACKAGE TO GROUND.

Figure 6. Pin Configuration

Rev. B | Page 9 of 24

ADV7619

Data Sheet

Table 5. Pin Function Descriptions

Pin No. Mnemonic

Type

Description

0

1

GND

Ground

Ground. Connect the exposed pad (Pin 0) on the bottom of the package to ground.

Ground.

2

3

4

5

±

7

8

9

CVDD

RXA_C−

RXA_C+

TVDD

RXA_0−

RXA_0+

TVDD

RXA_1−

RXA_1+

TVDD

RXA_2−

RXA_2+

CVDD

GND

TEST1

DVDD

TEST2

CVDD

RXB_C−

RXB_C+

TVDD

RXB_0−

RXB_0+

TVDD

RXB_1−

RXB_1+

TVDD

RXB_2−

RXB_2+

CVDD

GND

NC

DVDD

P47

P4±

P45

P44

P43

DVDDIO

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

Power

HDMI Analog Block Supply Voltage (1.8 V).

Digital Input Clock Complement of Port A in the HDMI Interface.

Digital Input Clock True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

Digital Input Channel 0 True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

Digital Input Channel 1 True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

Digital Input Channel 2 True of Port A in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

Ground.

HDMI input

Power

HDMI input

Power

HDMI input

Power

HDMI input

Power

10

11

12

13

14

15

1±

17

18

19

20

21

22

23

24

25

2±

27

28

29

30

31

32

33

34

35

3±

37

38

39

40

41

42

43

44

45

4±

47

48

49

50

51

Ground

Test

Power

Test

This pin must be left floating.

Digital Core Supply Voltage (1.8 V).

This pin must be left floating.

Power

HDMI Analog Block Supply Voltage (1.8 V).

Digital Input Clock Complement of Port B in the HDMI Interface.

Digital Input Clock True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 2 True of Port B in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

Ground.

No Connect. Do not connect to this pin.

Digital Core Supply Voltage (1.8 V).

Video Pixel Output Port.

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

HDMI input

Power

HDMI input

Power

HDMI input

Power

HDMI input

Power

Ground

No connect

Power

Digital video output

Power

Digital video output

Video Pixel Output Port.

P32

Rev. B | Page 10 of 24

Data Sheet

ADV7619

Pin No. Mnemonic

Type

Description

52

53

54

55

5±

57

58

59

±0

±1

±2

±3

±4

±5

±±

±7

±8

±9

70

71

72

73

74

75

7±

77

78

79

80

81

82

83

84

85

8±

87

88

89

90

91

92

93

94

95

DVDDIO

DVDD

P31

P30

P29

P28

P27

P2±

P25

P24

LLC

DVDD

DVDDIO

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

DVDDIO

P12

DVDD

P11

P10

P9

Power

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.8 V).

Video Pixel Output Port.

Pixel Output Clock for the Pixel Data. The range is from 13.5 MHz to 170 MHz.

Digital Core Supply Voltage (1.8 V).

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

Digital Core Supply Voltage (1.8 V).

Video Pixel Output Port.

Digital video output

Power

Digital video output

Power

Digital video output

Power

Digital video output

Power

P8

P7

P±

P5

P4

P3

P2

P1

P0

DVDDIO

DE

Digital I/O Supply Voltage (3.3 V).

Data Enable. The DE signal indicates active pixel data.

Horizontal Synchronization Output Signal.

VS is a vertical synchronization output signal. FIELD is a field synchronization output

signal in all interlaced video modes. ALSB allows selection of the I²C address.

Miscellaneous digital

Digital video output

HS

VS/FIELD/ALSB Digital video output

9±

97

98

99

100

NC

AP0

No connect

Miscellaneous

No Connect. Do not connect to this pin.

Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit

rate (HBR), or Direct Stream Digital® (DSD®).

101

AP1

Miscellaneous

Audio Output Pin/TDM I²S Output. This pin can be configured to output S/PDIF digital

audio, high bit rate (HBR), Direct Stream Digital (DSD).

Rev. B | Page 11 of 24

ADV7619

Data Sheet

Pin No. Mnemonic

Type

Description

102

103

104

105

10±

AP2

Miscellaneous

Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit

rate (HBR), Direct Stream Digital (DSD), or I²S.

Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit

rate (HBR), Direct Stream Digital (DSD), or I²S.

Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit

rate (HBR), Direct Stream Digital (DSD), or I²S.

Serial Clock/Interrupt 2. This dual-function pin can be configured to output the audio

serial clock or an Interrupt 2 signal.

AP3

Miscellaneous

AP4

Miscellaneous

SCLK/INT2

AP5

Miscellaneous digital

Miscellaneous

Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit

rate (HBR), or Direct Stream Digital (DSD). Pin AP5 is typically used to provide the

LRCLK for I²S modes.

107

MCLK/INT2

Miscellaneous digital

Master Clock/Interrupt 2. This dual-function pin can be configured to output the audio

master clock or an Interrupt 2 signal.

108

109

110

111

DVDD

SDA

SCL

Power

Digital Core Supply Voltage (1.8 V).

I²C Port Serial Data Input/Output Pin. SDA is the data line for the control port.

I²C Port Serial Clock Input. SCL is the clock line for the control port.

Interrupt. This pin can be active low or active high. When status bits change, this pin is

triggered. The events that trigger an interrupt are user configurable.

Miscellaneous digital

INT1

112

113

RESET

CS

Miscellaneous digital

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV7±19 circuitry.

Chip Select. This pin has an internal pull-down. Pulling this line up causes I²C state

machine to ignore I²C transmission.

114

115

PVDD

XTALP

Power

Miscellaneous

PLL Supply Voltage (1.8 V).

Input Pin for 28.±3±3± MHz Crystal or External 1.8 V, 28.±3±3± MHz Clock Oscillator

Source to Clock the ADV7±19.

11±

117

118

119

120

121

122

123

124

125

XTALN

DVDD

CEC

DDCB_SCL

DDCB_SDA

HPA_B

Miscellaneous

Power

Digital input/output

HDMI input

Miscellaneous digital

HDMI input

Miscellaneous digital

Crystal Input. Input pin for 28.±3±3± MHz crystal.

Digital Core Supply Voltage (1.8 V).

Consumer Electronics Control Channel.

HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.

Hot Plug Assert Signal Output for HDMI Port B.

5 V Detect Pin for Port B in the HDMI Interface.

HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.

RXB_5V

DDCA_SCL

DDCA_SDA

HPA_A/INT2

Hot Plug Assert/Interrupt 2. This dual-function pin can be configured to output the

Hot Plug assert signal for HDMI Port A or an Interrupt 2 signal.

12±

127

128

RXA_5V

NC

HDMI input

No connect

5 V Detect Pin for Port A in the HDMI Interface.

No Connect. Do not connect to this pin.

Rev. B | Page 12 of 24

Data Sheet

ADV7619

POWER SUPPLY RECOMMENDATIONS

POWER-UP SEQUENCE

POWER-DOWN SEQUENCE

The recommended power-up sequence for the ADV7619 is to

power up the 3.3 V supplies first, followed by the 1.8 V supplies.

The ADV7619 supplies can be deasserted simultaneously as long

as a higher rated supply does not go below a lower rated supply.

should be held low while the supplies are powered up.

RESET

CURRENT RATING REQUIREMENTS FOR POWER

SUPPLY DESIGN

Alternatively, the ADV7619 can be powered up by asserting all

supplies simultaneously. In this case, care must be taken while

the supplies are being established to ensure that a lower rated

supply does not go above a higher rated supply level.

Table 6 shows the current rating requirements for power supply

design.

Table 6. Current Rating Requirements for Power Supply Design

3.3V SUPPLIES

3.3V

Parameter

Current Rating (mA)

I_DVDD

I_DVDDIO

I_PVDD

400

300

50

1.8V SUPPLIES

I_TVDD

I_CVDD

120

250

1.8V

3.3V SUPPLIES

POWER-UP

1.8V SUPPLIES

POWER-UP

Figure 7. Recommended Power-Up Sequence

Rev. B | Page 13 of 24

ADV7619

Data Sheet

FUNCTIONAL OVERVIEW

•

CEC controller

HDMI RECEIVER

The HDMI receiver supports all mandatory and many optional

3D video formats defined in the HDMI 1.4a specification, HDTV

formats up to 2160p, and all display resolutions up to 4k × 2k

(3840 × 2160 at 30 Hz).

COMPONENT PROCESSOR (CP)

The ADV7619 has two any-to-any, 3 × 3 color space conversion

(CSC) matrices. The first CSC block is placed in front of the CP

section. The second CSC block is placed at the back of the CP

section. Each CSC enables YPrPb-to-RGB and RGB-to-YCrCb

conversions. Many other standards of color space can be imple-

mented using the color space converters.

With the inclusion of HDCP, displays can now receive encrypted

video content. The HDMI interface of the ADV7619 allows for

authentication of a video receiver, decryption of encoded data at

the receiver, and renewability of that authentication during trans-

mission, as specified by the HDCP 1.4 specification.

The CP block is available only for video signals with resolution

up to 1080p Deep Color (pixel rates up to 170 MHz). For resolu-

tions higher than 1080p, the video signal bypasses the CP block

and is routed directly to the pixel bus output as two 24-bit (4:4:4)

buses running at up to 150 MHz.

The HDMI-compatible receiver on the ADV7619 allows active

equalization of the HDMI data signals. This equalization compen-

sates for the high frequency losses inherent in HDMI and DVI

cabling, especially at longer cable lengths and higher frequencies.

The HDMI-compatible receiver is capable of equalizing for cable

lengths up to 30 meters to achieve robust receiver performance.

The ADV7619 also supports TERC4 error detection, which is

used for detection of corrupted HDMI packets following a cable

disconnect.

CP features include

•

Support for 525i, 625i, 525p, 625p, 720p, 1080i, 1080p,

and many other HDTV formats

Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation

Free-run output mode that provides stable timing when

no video input is present

170 MHz conversion rate, which supports RGB input

resolutions up to 1600 × 1200 at 60 Hz

The HDMI receiver offers advanced audio functionality. The

receiver contains an audio mute controller that can detect a variety

of conditions that may result in audible extraneous noise in the

audio output. Upon detection of these conditions, the audio signal

can be ramped down or muted to prevent audio clicks or pops.

The HDMI receiver supports the reception of all types of audio

data described in the HDMI specifications, including

•

Standard identification enabled by STDI block

RGB that can be color space converted to YCrCb and

decimated to a 4:2:2 format for video-centric, back-end

IC interfacing

•

LPCM (uncompressed audio)

IEC 61937 (compressed audio)

DSD audio (1-bit audio)

•

Data enable (DE) output signal supplied for direct

connection to HDMI/DVI transmitter

HBR audio (high bit rate compressed audio)

OTHER FEATURES

The ADV7619 has HS, VS, FIELD, and DE output signals with

programmable position, polarity, and width.

Xpressview fast switching can be implemented with full HDCP

authentication available on the background port. Synchroniza-

tion measurement and status information are available for all

HDMI inputs. HDMI receiver features include

The ADV7619 has two programmable interrupt request output

pins: INT1 and INT2 (INT2 is accessible via one of the following

pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2). The ADV7619

also features a low power power-down mode.

The main I²C address can be set to 0x98 or 0x9A. On power-up or

after a reset, the I²C address is set to 0x98 by default. The address

can be changed to 0x9A by pulling up the VS/FIELD/ALSB pin

and issuing the I²C command SAMPLE_ALSB. For more infor-

mation, see the Register Access and Serial Ports Description

section in the UG-237.

•

2:1 multiplexed HDMI receiver

3D format support

297 MHz HDMI receiver

Support for 4k × 2k resolutions

Integrated equalizer for cable lengths up to 30 meters

High-bandwidth Digital Content Protection (HDCP 1.4)

(on background ports, also)

•

Internal HDCP keys

The ADV7619 is provided in a 128-lead, 14 mm × 14 mm,

RoHS-compliant TQFP_EP package and is specified over the

0°C to 70°C temperature range.

36-/30-bit Deep Color support (resolutions up to 1080p)

Audio sample, HBR, DSD packet support

Repeater support

Internal EDID RAM

Hot Plug assert output pin for each HDMI port

Rev. B | Page 14 of 24

Data Sheet

ADV7619

PIXEL INPUT/OUTPUT FORMATTING

The output section of the ADV7619 is highly flexible. The pixel

output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4

RGB. For resolutions higher than 1080p, the pixel output bus

supports two 24-bit 4:4:4 RGB/YCrCb.

PIXEL DATA OUTPUT MODE FEATURES

For resolutions up to 1080p Deep Color, the output pixel port

features include the following:

•

SDR 8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embed-

ded time codes and/or HS, VS, and FIELD output signals

SDR 16-/20-/24-bit 4:2:2 YCrCb with embedded time codes

and/or HS and VS/FIELD pin timing

SDR 24-/30-/36-bit 4:4:4 YCrCb/RGB with embedded time

codes and/or HS and VS/FIELD pin timing

Part supports SDR (single data rate) and double data rate

(DDR) outputs. SDR is supported up to 170 MHz LLC

frequency (UXGA, 1080p60 for any OP_FORMAT_SEL or

up to 300 MHz HDMI signals output on two 24-bit parallel

video sub buses OP_FORMAT_SEL = 0x94, 0x95, 0x96, or

0x54; refer to Table 12). DDR can be supported with LLC clock

frequency up to 50 MHz (video modes with original pixel clock

lower than 100 MHz, such as 1080i60). In SDR mode, 16-/20-/

24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In DDR

mode, the pixel output port can be configured for 4:2:2 YCrCb

or 4:4:4 RGB for data rates up to 27 MHz.

•

DDR 8-/10-/12-bit 4:2:2 YCrCb for data rates up to 27 MHz

DDR 12-/24-/30-/36-bit 4:4:4 RGB for data rates up to

27 MHz

For resolutions greater than 1080p Deep Color (direct pass-

through of video signal), the output pixel port features include

the following:

Bus rotation is supported.

•

8-bit 4:4:4 RGB/YCrCb for resolutions up to 2160p

12-bit 4:2:2 RGB/YCrCb for resolutions up to 2160p

Table 7 through Table 12 provide the different output formats

that are supported. All output modes are controlled via I²C.

For resolutions higher than 1080p, the video signals are routed

directly to the pixel bus output as two 24-bit (4:4:4) buses running

at up to 150 MHz. In this mode, the output data format is the

same as the input format.

Rev. B | Page 15 of 24

ADV7619

Data Sheet

Table 7. SDR 4:2:2 Output Modes (8-/10-/12-Bit)¹

SDR 4:2:2—OP_FORMAT_SEL[7:0] =

0x00

0x01

0x02

0x06

0x0A

8-Bit SDR

ITU-R BT.656

Mode 0

10-Bit SDR

ITU-R BT.656

Mode 0

12-Bit SDR

ITU-R BT.656

Mode 0

12-Bit SDR

ITU-R BT.656

Mode 1

12-Bit SDR

ITU-R BT.656

Mode 2

Pixel Output

P47

P4±

P45

P44

P43

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

P32

P31

P30

P29

P28

P27

P2±

P25

P24

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

P12

P11

P10

P9

High-Z

Y7, Cb7, Cr7

Y±, Cb±, Cr±

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y±, Cb±, Cr±

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y11, Cb11, Cr11

Y10, Cb10, Cr10

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y±, Cb±, Cr±

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y11, Cb11, Cr11

Y10, Cb10, Cr10

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y±, Cb±, Cr±

Y5, Cb5, Cr5

Y4, Cb4, Cr4

Y3, Cb3, Cr3

Y2, Cb2, Cr2

High-Z

Y3, Cb3, Cr3

Y2, Cb2, Cr2

Y1, Cb1, Cr1

Y0, Cb0, Cr0

High-Z

Y11, Cb11, Cr11

Y10, Cb10, Cr10

Y9, Cb9, Cr9

Y8, Cb8, Cr8

Y7, Cb7, Cr7

Y±, Cb±, Cr±

Y5, Cb5, Cr5

Y4, Cb4, Cr4

High-Z

P8

High-Z

P7

High-Z

P±

High-Z

P5

High-Z

P4

High-Z

P3

High-Z

P2

High-Z

P1

High-Z

P0

High-Z

¹Modes require additional writes to IO map Register 0x19 (Bits[7:±] should be set to 2'b11) and IO map Register 0x33 (Bit[±] should be set to 1).

Rev. B | Page 1± of 24

Data Sheet

ADV7619

Table 8. SDR 4:2:2 Output Modes (16-/20-/24-Bit)

SDR 4:2:2—OP_FORMAT_SEL[7:0] =

0x80

0x81

0x82

0x86

0x8A

16-Bit SDR

ITU-R BT.656

Mode 0

20-Bit SDR

ITU-R BT.656

Mode 0

24-Bit SDR

ITU-R BT.656

Mode 0

24-Bit SDR

ITU-R BT.656

Mode 1

24-Bit SDR

ITU-R BT.656

Mode 2

Pixel Output

P47

P4±

P45

P44

P43

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

P32

P31

P30

P29

P28

P27

P2±

P25

P24

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

P12

P11

P10

P9

High-Z

Y7

Y±

Y5

Y4

Y3

Y2

Y1

Y0

High-Z

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Y9

High-Z

Y11

High-Z

Cb1, Cr1

Cb0, Cr0

High-Z

Y1

High-Z

Y3

Y2

Y1

Y0

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Y11

Y10

Y9

Y8

Y7

Y0

High-Z

Y11

Y10

Y9

Y8

Y7

Y±

Y5

Y4

Y3

Y8

Y7

Y±

Y5

Y4

Y3

Y2

Y1

Y10

Y9

Y8

Y7

Y±

Y5

Y4

Y3

Y±

Y5

Y4

High-Z

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

High-Z

Y0

Y2

Y1

Y0

Y2

High-Z

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

High-Z

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

P8

P7

P±

P5

P4

P3

P2

P1

P0

Rev. B | Page 17 of 24

ADV7619

Data Sheet

Table 9. SDR 4:4:4 Output Modes

SDR 4:4:4—OP_FORMAT_SEL[7:0] =

0x42

0x40

0x41

0x46

24-Bit SDR

Mode 0

30-Bit SDR

Mode 0

36-Bit SDR

Mode 0

36-Bit SDR

Mode 1

Pixel Output

P47

P4±

P45

P44

P43

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

P32

P31

P30

P29

P28

P27

P2±

P25

P24

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

P12

P11

P10

P9

High-Z

R7

R±

R5

R4

R3

R2

R1

R0

High-Z

G7

G±

G5

G4

G3

G2

G1

G0

High-Z

B7

High-Z

R9

R8

R7

R±

R5

R4

R3

R2

R1

High-Z

R11

R10

R9

R8

R7

R±

R5

R4

R3

R2

R1

High-Z

R9

R8

R7

R±

R5

R4

R3

R2

R1

R0

G7

G±

G5

G4

G3

G2

G1

High-Z

G9

G8

G7

G±

G5

G4

G3

G2

G1

G0

High-Z

B9

B8

B7

R0

G11

G10

G9

G8

G7

G±

G5

G4

G3

G2

G1

G0

B11

B10

B9

G0

B11

B10

B9

B8

G11

G10

B7

B±

B5

B±

B5

P8

B4

B±

B8

B4

P7

B3

B5

B7

B3

P±

B2

B4

B±

B2

P5

B1

B3

B5

B1

P4

B0

B2

B4

B0

P3

P2

P1

P0

High-Z

B1

B0

High-Z

B3

B2

B1

B0

R11

R10

G9

G8

Rev. B | Page 18 of 24

Data Sheet

ADV7619

Table 10. DDR 4:2:2 Output Modes

DDR 4:2:2 Mode (Clock/2)—OP_FORMAT_SEL[7:0] =

0x21

0x20

0x22

8-Bit DDR

ITU-R BT.656, Mode 0

10-Bit DDR

ITU-R BT.656, Mode 0

12-Bit DDR

ITU-R BT.656, Mode 0

Pixel Output

P47

P4±

P45

P44

P43

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

P32

P31

P30

P29

P28

P27

P2±

P25

P24

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

P12

P11

P10

P9

Clock Rise

Clock Fall

High-Z

Y7

Y±

Y5

Y4

Y3

Y2

Y1

Y0

High-Z

Clock Rise

High-Z

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Clock Fall

High-Z

Y9

Clock Rise

Clock Fall

High-Z

Y11

High-Z

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Cb11, Cr11

Cb10, Cr10

Cb9, Cr9

Cb8, Cr8

Cb7, Cr7

Cb±, Cr±

Cb5, Cr5

Cb4, Cr4

Cb3, Cr3

Cb2, Cr2

Cb1, Cr1

Cb0, Cr0

High-Z

Y8

Y7

Y±

Y5

Y4

Y3

Y2

Y1

Y10

Y9

Y8

Y7

Y±

Y5

Y4

Y3

Y0

Y2

Y1

Y0

High-Z

P8

P7

P±

P5

P4

P3

P2

P1

P0

Rev. B | Page 19 of 24

ADV7619

Data Sheet

Table 11. DDR 4:4:4 Output Modes

DDR 4:4:4 Mode (Clock/2)—OP_FORMAT_SEL[7:0] =

0x60

24-Bit DDR, Mode 0

0x61

30-Bit DDR, Mode 0

Pixel Output

P47

P4±

P45

P44

P43

P42

P41

P40

P39

P38

P37

P3±

P35

P34

P33

P32

P31

P30

P29

P28

P27

P2±

P25

P24

P23

P22

P21

P20

P19

P18

P17

P1±

P15

P14

P13

P12

P11

P10

P9

Clock Rise¹

Clock Fall¹

High-Z

R7-1

Clock Rise¹

High-Z

R9-0

Clock Fall¹

High-Z

R9-1

High-Z

R7-0

High-Z

R11-0

R10-0

R9-0

R±-0

R5-0

R±-1

R5-1

R8-0

R7-0

R8-1

R7-1

R4-0

R3-0

R2-0

R1-0

R4-1

R3-1

R2-1

R1-1

R±-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

High-Z

G9-0

G8-0

G7-0

G±-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

High-Z

B9-0

B8-0

B7-0

R±-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

High-Z

G9-1

G8-1

G7-1

G±-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

High-Z

B9-1

B8-1

B7-1

R8-0

R7-0

R±-0

R5-0

R4-0

R3-0

R2-0

R1-0

R8-1

R7-1

R±-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-0

R0-1

High-Z

G7-0

G±-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

High-Z

B7-0

High-Z

G7-1

G±-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

High-Z

B7-1

R0-0

R0-1

G11-0

G10-0

G9-0

G8-0

G7-0

G±-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

B11-0

B10-0

B9-0

G11-1

G10-1

G9-1

G8-1

G7-1

G±-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B11-1

B10-1

B9-1

B±-0

B5-0

B±-1

B5-1

P8

B4-0

B4-1

B±-0

B±-1

B8-0

B8-1

P7

B3-0

B3-1

B5-0

B5-1

B7-0

B7-1

P±

B2-0

B2-1

B4-0

B4-1

B±-0

B±-1

P5

B1-0

B1-1

B3-0

B3-1

B5-0

B5-1

P4

B0-0

B0-1

B2-0

B2-1

B4-0

B4-1

P3

P2

P1

P0

High-Z

B1-0

B0-0

High-Z

B1-1

B0-1

High-Z

B3-0

B2-0

B1-0

B0-0

B3-1

B2-1

B1-1

B0-1

¹xx-0 and xxx-0 correspond to data clocked at the rising edge; xx-1 and xxx-1 correspond to data clocked at the falling edge.

Rev. B | Page 20 of 24

Data Sheet

ADV7619

Table 12. Special SDR 4:2:2 and 4:4:4 Output Modes for Video with Pixel Clock Frequencies Above 170 MHz¹

2 × SDR 4:2:2 Interleaved—OP_FORMAT_SEL[7:0] =

2 × SDR 4:4:4 Interleaved—OP_FORMAT_SEL[7:0] =

0x94

0x95

0x96

0x54

2 × 20-Bit

Mode 0²

2 × 24-Bit

Mode 0²

2 × 24-Bit

Mode 0²

2 × 16-Bit

Mode 0²

Pixel Output

P47

P46

P45

P44

P43

P42

P41

P40

P39

P38

P37

P36

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

P25

P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14

P13

P12

P11

P10

P9

Y7-0

Y6-0

Y5-0

Y4-0

Y3-0

Y2-0

Y1-0

Y0-0

High-Z

Cb7-0

Cb6-0

Cb5-0

Cb4-0

Cb3-0

Cb2-0

Cb1-0

Cb0-0

High-Z

Y7-1

Y6-1

Y5-1

Y4-1

Y3-1

Y2-1

Y1-1

Y0-1

High-Z

Cr7-0

Cr6-0

Cr5-0

Cr4-0

Cr3-0

Cr2-0

Cr1-0

Cr0-0

High-Z

Y9-0

Y8-0

Y7-0

Y6-0

Y5-0

Y4-0

Y3-0

Y2-0

Y11-0

Y10-0

Y9-0

Y8-0

Y7-0

Y6-0

Y5-0

Y4-0

Y3-0

G7-0

G6-0

G5-0

G4-0

G3-0

G2-0

G1-0

G0-0

B7-0

B6-0

B5-0

B4-0

B3-0

B2-0

B1-0

B0-0

R7-0

R6-0

R5-0

R4-0

R3-0

R2-0

R1-0

R0-0

G7-1

G6-1

G5-1

G4-1

G3-1

G2-1

G1-1

G0-1

B7-1

B6-1

B5-1

B4-1

B3-1

B2-1

B1-1

B0-1

R7-1

R6-1

R5-1

R4-1

R3-1

R2-1

R1-1

R0-1

Y1-0

Y0-0

Y2-0

Y1-0

Y0-0

High-Z

Cb9-0

Cb8-0

Cb7-0

Cb6-0

Cb5-0

Cb4-0

Cb3-0

Cb2-0

Cb1-0

Cb0-0

High-Z

Y9-1

Y8-1

Y7-1

Y6-1

Y5-1

Y4-1

Y3-1

Y2-1

Y1-1

Cb11-0

Cb10-0

Cb9-0

Cb8-0

Cb7-0

Cb6-0

Cb5-0

Cb4-0

Cb3-0

Cb2-0

Cb1-0

Cb0-0

Y11-1

Y10-1

Y9-1

Y8-1

Y7-1

Y6-1

Y5-1

Y4-1

Y3-1

Y2-1

Y1-1

Y0-1

High-Z

Cr9-0

Cr8-0

Cr7-0

Cr6-0

Cr5-0

Cr4-0

Cr3-0

Cr2-0

Cr1-0

Cr0-0

High-Z

Y0-1

Cr11-0

Cr10-0

Cr9-0

Cr8-0

Cr7-0

Cr6-0

Cr5-0

Cr4-0

Cr3-0

Cr2-0

Cr1-0

Cr0-0

P8

P7

P6

P5

P4

P3

P2

P1

P0

¹These modes require additional writes. (write 80 to DPLL map Register 0xC3, write 03 to DPLL map Register 0xCF, and write A0 to IO map Register 0xDD). Refer to

Hardware User Guide UG-237.

²xx-0 and xxx-0 correspond to odd samples; xx-1 and xxx-1 correspond to even samples.

Rev. B | Page 21 of 24

ADV7619

Data Sheet

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

1.20

MAX

14.20

14.00 SQ

13.80

0.75

0.60

0.45

12.40 REF

128

97

96

97

96

128

1

1.00 REF

PIN 1

SEATING

PLANE

EXPOSED

PAD

6.35

REF

TOP VIEW

BOTTOM VIEW

(PINS UP)

1.05

1.00

0.95

(PINS DOWN)

0.20

0.15

0.09

32

65

64

65

64

32

33

0.23

0.18

0.13

VIEW A

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.15

0.10

0.05

0.40

BSC

LEAD PITCH

7°

0°

0.08

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AEE-HD

ROTATED 90° CCW

Figure 8. 128-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-128-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

ADV7±19KSVZ

Temperature Range

0°C to 70°C

Package Description

128-Lead TQFP_EP

Package Option

SV-128-1

ADV7±19KSVZ-P

EVAL-ADV7±19EB1Z

EVAL-ADV7±19-7511-P

EVAL-ADV7±19-7511

Evaluation Board with HDCP key

Evaluation Board without HDCP keys

Evaluation Board with HDCP keys

¹Z = RoHS Compliant Part.

²EVAL-ADV7±19-7511 and EVAL-ADV7±19-7511-P are RoHS Compliant Parts.

Rev. B | Page 22 of 24

Data Sheet

NOTES

ADV7619

Rev. B | Page 23 of 24

ADV7619

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries.

registered trademarks are the property of their respective owners.

D09580-0-5/12(B)

Rev. B | Page 24 of 24

型号:	ADV7619KSVZ
Source Url Status Check Date：	2013-05-01 14:56:51.977
Brand Name：	Analog Devices Inc
是否无铅：	含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFP
包装说明：	HTFQFP,
针数：	128
制造商包装代码：	SV-128-1
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.63
JESD-30 代码：	S-PQFP-G128
JESD-609代码：	e3
长度：	14 mm
湿度敏感等级：	3
功能数量：	1
端子数量：	128
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTFQFP
封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1.2 mm
标称供电电压：	1.8 V
表面贴装：	YES
技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.4 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

电子百科

产品导航

产品型号ADV7619KSVZ的概述

产品型号ADV7619KSVZ的Datasheet PDF文件预览

ADV7619KSVZ相关产品

ADV7619KSVZ相关文章

IC37:专业IC行业平台