AT89C51现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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产品型号AT89C51的概述

AT89C51芯片概述 AT89C51是Atmel公司生产的一个基于8051架构的8位单片机。该芯片以其简单易用、高度灵活和低功耗等特性广泛应用于各种嵌入式系统。8051架构自20世纪80年代问世以来，经过多年的发展，仍旧在许多现代电子项目中扮演着重要角色。AT89C51单片机不仅继承了8051架构的优点，而且融入了现代设计的诸多创新，使其在性能和功能上有了显著提升。 AT89C51单片机在许多领域都得到了广泛应用，尤其是在消费电子、工业控制、家用电器和汽车电子等领域。凭借较高的性能，AT89C51成为了单片机开发者和爱好者们的热门选择。其简单的结构以及丰富的外设接口，使得程序设计和硬件开发都相对容易，降低了开发难度，适合于入门学习和实际工程应用。 AT89C51的详细参数 AT89C51的主要技术参数如下： - 处理器类型：8051架构的8位微控制器 - 时钟速度：最大工作频率为12...

产品型号AT89C51的Datasheet PDF文件预览

Features

• Compatible with MCS-51™ Products

• 4K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz

• Three-Level Program Memory Lock

• 128 x 8-Bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-Bit Timer/Counters

• Six Interrupt Sources

• Programmable Serial Channel

• Low Power Idle and Power Down Modes

8-Bit

Microcontroller

with 4K Bytes

Flash

Description

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K

bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The

device is manufactured using Atmel’s high density nonvolatile memory technology

and is compatible with the industry standard MCS-51™ instruction set and pinout. The

on-chip Flash allows the program memory to be reprogrammed in-system or by a con-

ventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with

Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which

provides a highly flexible and cost effective solution to many embedded control appli-

AT89C51

cations.

(continued)

PDIP

Pin Configurations

P 1 . 0

P 1 . 1

P 1 . 2

P 1 . 3

P 1 . 4

P 1 . 5

P 1 . 6

P 1 . 7

R S T

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

V C C

P 0 . 0 ( A D 0 )

P 0 . 1 ( A D 1 )

P 0 . 2 ( A D 2 )

P 0 . 3 ( A D 3 )

P 0 . 4 ( A D 4 )

P 0 . 5 ( A D 5 )

P 0 . 6 ( A D 6 )

P 0 . 7 ( A D 7 )

E A / V P P

( R X D ) P 3 . 0

( T X D ) P 3 . 1

( I N T 0 ) P 3 . 2

( I N T 1 ) P 3 . 3

( T 0 ) P 3 . 4

( T 1 ) P 3 . 5

( W R ) P 3 . 6

( R D ) P 3 . 7

X TA L 2

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

PQFP/TQFP

A L E / P R O G

P S E N

P 2 . 7 ( A 1 5 )

P 2 . 6 ( A 1 4 )

P 2 . 5 ( A 1 3 )

P 2 . 4 ( A 1 2 )

P 2 . 3 ( A 1 1 )

P 2 . 2 ( A 1 0 )

P 2 . 1 ( A 9 )

P 2 . 0 ( A 8 )

I N D E X

C O R N E R

4 4 4 2 4 0 3 8 3 6 3 4

4 3 4 1 3 9 3 7 3 5

X TA L 1

G N D

P 0 . 4 ( A D 4 )

P 0 . 5 ( A D 5 )

P 0 . 6 ( A D 6 )

P 0 . 7 ( A D 7 )

P 1 . 5

P 1 . 6

P 1 . 7

3 3

3 2

3 1

3 0

2 9

PLCC

R S T

( R X D ) P 3 . 0

N C

( T X D ) P 3 . 1

( I N T 0 ) P 3 . 2

( I N T 1 ) P 3 . 3

( T 0 ) P 3 . 4

( T 1 ) P 3 . 5

E A / V P P

N C

A L E / P R O G

P S E N

P 2 . 7 ( A 1 5 )

P 2 . 6 ( A 1 4 )

P 2 . 5 ( A 1 3 )

2 8

2 7

2 6

2 5

2 4

2 3

I N D E X

C O R N E R

1 0

1 1

4 4 4 2 4 0

1 9

1 8 2 0 2 2

1 3 1 5 1 7

2 1

4 3 4 1

3 9

P 1 . 5

P 0 . 4 ( A D 4 )

P 0 . 5 ( A D 5 )

P 0 . 6 ( A D 6 )

P 0 . 7 ( A D 7 )

E A / V P P

1 6

1 2 1 4

P 1 . 6

P 1 . 7

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

R S T

( R X D ) P 3 . 0

N C

( T X D ) P 3 . 1

( I N T 0 ) P 3 . 2

( I N T 1 ) P 3 . 3

( T 0 ) P 3 . 4

N C

A L E / P R O G

P S E N

P 2 . 7 ( A 1 5 )

P 2 . 6 ( A 1 4 )

P 2 . 5 ( A 1 3 )

( T 1 ) P 3 . 5

1 9 2 1 2 3 2 5 2 7

2 8

1 8 2 0 2 2 2 4 2 6

0265F-A–12/97

4-29

Block Diagram

P0.0 - P0.7

P2.0 - P2.7

V_CC

PORT 0 DRIVERS

PORT 2 DRIVERS

GND

RAM ADDR.

PORT 0

LATCH

PORT 2

LATCH

RAM

FLASH

PROGRAM

ADDRESS

STACK

POINTER

ACC

BUFFER

TMP2

TMP1

INCREMENTER

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM

COUNTER

PSW

PSEN

TIMING

AND

CONTROL

ALE/PROG

INSTRUCTION

DPTR

EA / V_PP

RST

PORT 1

LATCH

PORT 3

LATCH

OSC

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3 DRIVERS

P3.0 - P3.7

AT89C51

4-30

AT89C51

The AT89C51 provides the following standard features: 4K

bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit

timer/counters, a five vector two-level interrupt architecture,

a full duplex serial port, on-chip oscillator and clock cir-

cuitry. In addition, the AT89C51 is designed with static logic

for operation down to zero frequency and supports two

software selectable power saving modes. The Idle Mode

stops the CPU while allowing the RAM, timer/counters,

serial port and interrupt system to continue functioning. The

Power Down Mode saves the RAM contents but freezes

the oscillator disabling all other chip functions until the next

hardware reset.

when emitting 1s. During accesses to external data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the

contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some

control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source

current (I_IL) because of the pullups.

Port 3 also serves the functions of various special features

of the AT89C51 as listed below:

Pin Description

V_CC

Supply voltage.

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Functions

RXD (serial input port)

GND

Ground.

TXD (serial output port)

Port 0

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port each pin can sink eight TTL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 may also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memory. In this mode P0 has internal pul-

lups.

Port 3 also receives some control signals for Flash pro-

gramming and verification.

Port 0 also receives the code bytes during Flash program-

ming, and outputs the code bytes during program verifica-

tion. External pullups are required during program verifica-

tion.

RST

Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.

The Port 1 output buffers can sink/source four TTL inputs.

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally being pulled low will source

current (I_IL) because of the internal pullups.

ALE/PROG

Address Latch Enable output pulse for latching the low byte

of the address during accesses to external memory. This

pin is also the program pulse input (PROG) during Flash

programming.

In normal operation ALE is emitted at a constant rate of 1/6

the oscillator frequency, and may be used for external tim-

ing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external Data Mem-

ory.

Port 1 also receives the low-order address bytes during

Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.

The Port 2 output buffers can sink/source four TTL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally being pulled low will source

current (I_IL) because of the internal pullups.

If desired, ALE operation can be disabled by setting bit 0 of

SFR location 8EH. With the bit set, ALE is active only dur-

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @

DPTR). In this application it uses strong internal pullups

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

4-31

When the AT89C51 is executing code from external pro-

gram memory, PSEN is activated twice each machine

It should be noted that when idle is terminated by a hard

ware reset, the device normally resumes program execu-

tion, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to external

memory.

cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/V_PP

External Access Enable. EA must be strapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

Figure 1. Oscillator Connections

EA should be strapped to V_CCfor internal program execu-

tions.

This pin also receives the 12-volt programming enable volt-

age (V_PP) during Flash programming, for parts that require

XTAL2

12-volt V_PP

XTAL1

Input to the inverting oscillator amplifier and input to the

internal clock operating circuit.

XTAL1

XTAL2

Output from the inverting oscillator amplifier.

GND

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively,

of an inverting amplifier which can be configured for use as

an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is through a divide-by-two flip-flop, but minimum and maxi-

mum voltage high and low time specifications must be

observed.

Note:

C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 2. External Clock Drive Configuration

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-

chip peripherals remain active. The mode is invoked by

software. The content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Status of External Pins During Idle and Power Down Modes

Mode

Program Memory

Internal

ALE

PSEN

PORT0

Data

PORT1

Data

PORT2

Data

PORT3

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

External

Float

Data

AT89C51

4-32

AT89C51

Power Down Mode

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chip

RAM. The reset should not be activated before V_CCis

restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and sta-

bilize.

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device to

function properly.

Lock Bit Protection Modes

Program Lock Bits

Protection Type

LB1

LB2

LB3

No program lock features.

MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA is sampled and latched on reset, and further programming of the

Flash is disabled.

Same as mode 2, also verify is disabled.

Same as mode 3, also external execution is disabled.

Programming Algorithm: Before programming the

AT89C51, the address, data and control signals should be

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interface

accepts either a high-voltage (12-volt) or a low-voltage

(V_CC) program enable signal. The low voltage program-

ming mode provides a convenient way to program the

AT89C51 inside the user’s system, while the high-voltage

programming mode is compatible with conventional third

party Flash or EPROM programmers.

set up according to the Flash programming mode table and

Figures 3 and 4. To program the AT89C51, take the follow-

ing steps.

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/V_PPto 12V for the high-voltage programming

mode.

The AT89C51 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-side marking and device signature codes are listed in

the following table.

5. Pulse ALE/PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed

and typically takes no more than 1.5 ms. Repeat steps

1 through 5, changing the address and data for the

entire array or until the end of the object file is reached.

V_PP= 12V

V_PP= 5V

Top-Side Mark

Signature

AT89C51

xxxx

AT89C51

xxxx-5

yyww

Data Polling: The AT89C51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cycle

yyww

(030H)=1EH

(031H)=51H

(032H)=FFH

(030H)=1EH

(031H)=51H

(032H)=05H

has been completed, true data are valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

The AT89C51 code memory array is programmed byte-by-

byte in either programming mode. To program any non-

blank byte in the on-chip Flash Memory, the entire memory

must be erased using the Chip Erase Mode.

Ready/Busy: The progress of byte programming can also

be monitored by the RDY/BSY output signal. P3.4 is pulled

low after ALE goes high during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

4-33

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the address and data lines for verification. The lock bits

cannot be verified directly. Verification of the lock bits is

achieved by observing that their features are enabled.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming

Chip Erase: The entire Flash array is erased electrically

by using the proper combination of control signals and by

holding ALE/PROG low for 10 ms. The code array is written

with all “1”s. The chip erase operation must be executed

before the code memory can be re-programmed.

Programming Interface

Every code byte in the Flash array can be written and the

entire array can be erased by using the appropriate combi-

nation of control signals. The write operation cycle is self-

timed and once initiated, will automatically time itself to

completion.

Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of

locations 030H,

All major programming vendors offer worldwide support for

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

031H, and 032H, except that P3.6 and P3.7 must be pulled

to a logic low. The values returned are as follows.

Flash Programming Modes

Mode

RST

PSEN

ALE/PROG

EA/V_PP

P2.6

P2.7

P3.6

P3.7

Write Code Data

H/12V

Read Code Data

Write Lock

Bit - 1

Bit - 2

Bit - 3

H/12V

Chip Erase

(1)

Read Signature Byte

Note:

1. Chip Erase requires a 10-ms PROG pulse.

AT89C51

4-34

AT89C51

Figure 3. Programming the Flash

AT89C51

Figure 4. Verifying the Flash

+5V

AT89C51

A0 - A7

OOOOH/OFFFH

A8 - A11

A0 - A7

OOOOH/0FFFH

A8 - A11

V_CC

ADDR.

PGM DATA

(USE 10K

PULLUPS)

PGM

DATA

P2.0 - P2.3

P2.6

P2.0 - P2.3

P2.6

P2.7

ALE

SEE FLASH

PROGRAMMING

MODES TABLE

SEE FLASH

PROGRAMMING

MODES TABLE

P2.7

ALE

PROG

P3.6

V_IH

P3.7

XTAL2

V_IH/V_PP

XTAL2

3-24 MHz

V_IH

XTAL1

GND

RST

V_IH

XTAL1

GND

RST

PSEN

Flash Programming and Verification Characteristics

T_A= 0°C to 70°C, V_CC= 5.0 ± 10%

Symbol

Parameter

Min

Max

12.5

1.0

Units

(1)

V_PP

Programming Enable Voltage

Programming Enable Current

Oscillator Frequency

11.5

(1)

I_PP

1/t_CLCL

t_AVGL

MHz

Address Setup to PROG Low

Address Hold After PROG

Data Setup to PROG Low

Data Hold After PROG

P2.7 (ENABLE) High to V_PP

V_PPSetup to PROG Low

V_PPHold After PROG

PROG Width

48t_CLCL

t_GHAX

t_DVGL

t_GHDX

t_EHSH

t_SHGL

µs

(1)

t_GHSL

t_GLGH

t_AVQV

t_ELQV

t_EHQZ

t_GHBL

t_WC

110

Address to Data Valid

ENABLE Low to Data Valid

Data Float After ENABLE

PROG High to BUSY Low

Byte Write Cycle Time

48t_CLCL

1.0

µs

2.0

Note: 1. Only used in 12-volt programming mode.

4-35

Flash Programming and Verification Waveforms - High Voltage Mode (V = 12V)

PROGRAMMING

VERIFICATION

P1.0 - P1.7

P2.0 - P2.3

ADDRESS

t_AVQV

PORT 0

DATA IN

DATA OUT

t_DVGLt_GHDX

t_AVGL

t_GHAX

ALE/PROG

t_SHGL

t_GHSL

t_GLGH

V_PP

LOGIC 1

LOGIC 0

EA/V_PP

t_EHSH

t_EHQZ

t_ELQV

P2.7

(ENABLE)

t_GHBL

P3.4

(RDY/BSY)

BUSY

t_WC

READY

Flash Programming and Verification Waveforms - Low Voltage Mode (V = 5V)

PROGRAMMING

VERIFICATION

P1.0 - P1.7

P2.0 - P2.3

ADDRESS

t_AVQV

PORT 0

DATA IN

DATA OUT

t_DVGLt_GHDX

t_AVGL

t_GHAX

ALE/PROG

t_SHGL

t_GLGH

LOGIC 1

LOGIC 0

EA/V_PP

t_EHSH

t_EHQZ

t_ELQV

P2.7

(ENABLE)

t_GHBL

P3.4

(RDY/BSY)

BUSY

t_WC

READY

AT89C51

4-36

AT89C51

Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage............................................. 6.6V

DC Output Current...................................................... 15.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 5.0V ± 20% (unless otherwise noted)

Symbol

Parameter

Condition

Min

-0.5

Max

0.2 V - 0.1

Units

Input Low Voltage

Input Low Voltage (EA)

Input High Voltage

(Except EA)

0.2 V - 0.3

IL1

(Except XTAL1, RST)

(XTAL1, RST)

0.2 V + 0.9

+ 0.5

0.7 V

IH1

OL1

(1)

Output Low Voltage (Ports 1,2,3)

= 1.6 mA

= 3.2 mA

0.45

(1)

Output Low Voltage

0.45

(Port 0, ALE, PSEN)

Output High Voltage

(Ports 1,2,3, ALE, PSEN)

= -60 µA, V = 5V ± 10%

2.4

= -25 µA

= -10 µA

0.75 V

0.9 V

Output High Voltage

(Port 0 in External Bus Mode)

= -800 µA, V = 5V ± 10%

2.4

OH1

= -300 µA

0.75 V

= -80 µA

0.9 V

Logical 0 Input Current (Ports 1,2,3)

= 0.45V

-50

µA

Logical 1 to 0 Transition Current

(Ports 1,2,3)

= 2V, VCC = 5V ± 10%

-650

Input Leakage Current (Port 0, EA)

Reset Pulldown Resistor

Pin Capacitance

0.45 < V < V

±10

300

µA

KΩ

RRST

Test Freq. = 1 MHz, T = 25°C

Power Supply Current

Active Mode, 12 MHz

Idle Mode, 12 MHz

µA

(2)

Power Down Mode

= 6V

= 3V

100

Notes: 1. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port: Port 0: 26 mA

Ports 1, 2, 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimum V_CCfor Power Down is 2V.

4-37

AC Characteristics

(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other

outputs = 80 pF)

External Program and Data Memory Characteristics

Symbol

Parameter

12 MHz Oscillator

16 to 24 MHz Oscillator

Units

Min

Max

Min

Max

1/t_CLCL

t_LHLL

t_AVLL

t_LLAX

t_LLIV

Oscillator Frequency

MHz

ALE Pulse Width

127

2t_CLCL-40

t_CLCL-13

t_CLCL-20

Address Valid to ALE Low

Address Hold After ALE Low

ALE Low to Valid Instruction In

ALE Low to PSEN Low

PSEN Pulse Width

233

4t_CLCL-65

t_LLPL

t_CLCL-13

t_PLPH

t_PLIV

205

3t_CLCL-20

PSEN Low to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

RD Pulse Width

145

3t_CLCL-45

t_CLCL-10

t_PXIX

t_PXIZ

t_PXAV

t_AVIV

t_CLCL-8

312

5t_CLCL-55

t_PLAZ

t_RLRH

t_WLWH

t_RLDV

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

t_LLWL

t_AVWL

t_QVWX

t_QVWH

t_WHQX

t_RLAZ

t_WHLH

400

6t_CLCL-100

WR Pulse Width

RD Low to Valid Data In

Data Hold After RD

252

5t_CLCL-90

Data Float After RD

2t_CLCL-28

8t_CLCL-150

9t_CLCL-165

3t_CLCL+50

ALE Low to Valid Data In

Address to Valid Data In

ALE Low to RD or WR Low

Address to RD or WR Low

Data Valid to WR Transition

Data Valid to WR High

517

585

300

200

203

3t_CLCL-50

4t_CLCL-75

t_CLCL-20

433

7t_CLCL-120

t_CLCL-20

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE High

123

t_CLCL-20

t_CLCL+25

AT89C51

4-38

AT89C51

External Program Memory Read Cycle

t_LHLL

ALE

t_PLPH

t_AVLL

t_LLIV

t_PLIV

t_LLPL

PSEN

t_PXAV

t_PLAZ

t_PXIZ

t_PXIX

t_LLAX

A0 - A7

INSTR IN

A0 - A7

PORT 0

PORT 2

t_AVIV

A8 - A15

External Data Memory Read Cycle

t_LHLL

ALE

t_WHLH

PSEN

t_LLDV

t_RLRH

t_LLWL

t_LLAX

t_RHDZ

t_RHDX

t_RLDV

t_AVLL

t_RLAZ

A0 - A7 FROM RI OR DPL

DATA IN

A0 - A7 FROM PCL

INSTR IN

PORT 0

t_AVWL

t_AVDV

P2.0 - P2.7 OR A8 - A15 FROM DPH

A8 - A15 FROM PCH

PORT 2

4-39

External Data Memory Write Cycle

t_LHLL

ALE

t_WHLH

PSEN

t_LLWL

t_WLWH

t_LLAX

t_QVWX

t_WHQX

t_AVLL

t_QVWH

A0 - A7 FROM RI OR DPL

DATA OUT

A0 - A7 FROM PCL

INSTR IN

PORT 0

PORT 2

t_AVWL

P2.0 - P2.7 OR A8 - A15 FROM DPH

A8 - A15 FROM PCH

External Clock Drive Waveforms

t_CHCX

t_CLCH

t_CHCL

V_CC- 0.5V

0.7 V_CC

0.2 V_CC- 0.1V

0.45V

t_CLCX

t_CLCL

External Clock Drive

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

Max

Units

MHz

41.6

t_CHCX

t_CLCX

Low Time

t_CLCH

Rise Time

t_CHCL

Fall Time

AT89C51

4-40

AT89C51

Serial Port Timing: Shift Register Mode Test Conditions

(V_CC= 5.0 V ± 20%; Load Capacitance = 80 pF)

Symbol

Parameter

12 MHz Osc

Variable Oscillator

Units

Min

1.0

700

Max

Min

Max

t_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

Serial Port Clock Cycle Time

12t_CLCL

10t_CLCL-133

2t_CLCL-117

µs

Output Data Setup to Clock Rising Edge

Output Data Hold After Clock Rising Edge

Input Data Hold After Clock Rising Edge

Clock Rising Edge to Input Data Valid

700

10t_CLCL-133

Shift Register Mode Timing Waveforms

INSTRUCTION

ALE

t_XLXL

CLOCK

t_QVXH

t_XHQX

WRITE TO SBUF

t_XHDX

SET TI

t_XHDV

OUTPUT DATA

CLEAR RI

VALID

SET RI

INPUT DATA

(1)

AC Testing Input/Output Waveforms

Float Waveforms

V_CC- 0.5V

+ 0.1V

- 0.1V

V_OL

V_LOAD

0.2 V_CC+ 0.9V

Timing Reference

Points

V_LOAD

TEST POINTS

- 0.1V

0.2 V_CC- 0.1V

0.45V

V_LOAD

+ 0.1V

V_OL

Note:

1. AC Inputs during testing are driven at V_CC- 0.5V for Note:

a logic 1 and 0.45V for a logic 0. Timing measure-

ments are made at V_IHmin. for a logic 1 and V_IL

max. for a logic 0.

1. For timing purposes, a port pin is no longer floating

when a 100 mV change from load voltage occurs. A

port pin begins to float when 100 mV change from

the loaded V /V level occurs.

OH OL

4-41

Ordering Information

Speed

(MHz)

Power

Supply

Ordering Code

AT89C51-12AC

AT89C51-12JC

AT89C51-12PC

AT89C51-12QC

AT89C51-12AI

AT89C51-12JI

AT89C51-12PI

AT89C51-12QI

AT89C51-12AA

AT89C51-12JA

AT89C51-12PA

AT89C51-12QA

AT89C51-16AC

AT89C51-16JC

AT89C51-16PC

AT89C51-16QC

AT89C51-16AI

AT89C51-16JI

AT89C51-16PI

AT89C51-16QI

AT89C51-16AA

AT89C51-16JA

AT89C51-16PA

AT89C51-16QA

AT89C51-20AC

AT89C51-20JC

AT89C51-20PC

AT89C51-20QC

AT89C51-20AI

AT89C51-20JI

AT89C51-20PI

AT89C51-20QI

Package

44A

Operation Range

Commercial

5V ± 20%

44J

(0°C to 70°C)

40P6

44Q

44A

Industrial

44J

(-40°C to 85°C)

40P6

44Q

44A

Automotive

44J

(-40°C to 105°C)

40P6

44Q

44A

Commercial

44J

(0°C to 70°C)

40P6

44Q

44A

Industrial

44J

(-40°C to 85°C)

40P6

44Q

44A

Automotive

44J

(-40°C to 105°C)

40P6

44Q

44A

Commercial

44J

(0°C to 70°C)

40P6

44Q

44A

Industrial

44J

(-40°C to 85°C)

40P6

44Q

AT89C51

4-42

AT89C51

Ordering Information

Speed

(MHz)

Power

Supply

Ordering Code

AT89C51-24AC

AT89C51-24JC

AT89C51-24PC

AT89C51-24QC

AT89C51-24AI

AT89C51-24JI

AT89C51-24PI

AT89C51-24QI

Package

44A

Operation Range

5V ± 20%

Commercial

44J

(0°C to 70°C)

44P6

44Q

44A

Industrial

44J

(-40°C to 85°C)

44P6

44Q

Package Type

44A

44J

44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44 Lead, Plastic J-Leaded Chip Carrier (PLCC)

40P6

44Q

40 Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)

4-43

AT89C51相关文章

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AT89C51-12AC产品参数

型号:	AT89C51-12AC
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	ATMEL CORP
零件包装代码：	QFP
包装说明：	TQFP, TQFP44,.47SQ,32
针数：	44
Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01
风险等级：	5.79
Is Samacsys：	N
具有ADC：	NO
地址总线宽度：	16
位大小：	8
CPU系列：	8051
最大时钟频率：	24 MHz
DAC 通道：	NO
DMA 通道：	NO
外部数据总线宽度：	8
JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0
长度：	10 mm
I/O 线路数量：	32
端子数量：	44
最高工作温度：	70 °C
最低工作温度：
PWM 通道：	NO
封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP
封装等效代码：	TQFP44,.47SQ,32
封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	240
电源：	5 V
认证状态：	Not Qualified
RAM（字节）：	128
ROM（单词）：	4096
ROM可编程性：	FLASH
座面最大高度：	1.2 mm
速度：	12 MHz
子类别：	Microcontrollers
最大压摆率：	20 mA
最大供电电压：	6 V
最小供电电压：	4 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	30
宽度：	10 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

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