CD40174BCN原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号CD40174BCN的概述

芯片CD40174BCN的概述 CD40174BCN是一款来自德州仪器（Texas Instruments）公司的7位静态存储器，它属于CD4000系列的集成电路，广泛应用于数字电路中。CD40174作为一种双D触发器，设计用于存储二进制数据，能够在控制信号的作用下锁存输入并提供输出。该芯片的工作原理依赖于触发器（flip-flops），其特性的存储能力使得在逻辑电路中极为重要，尤其是在需要状态存储和数据寄存的场合。 CD40174BCN系列可以在宽广的电源电压范围（3V至15V）内工作，使其具有相对较高的适应性。此外，由于其输入兼容TTL（晶体管-晶体管逻辑），CD40174在多种电路系统中都得到了广泛应用，包括微控制器、数据路径、储存器等典型应用场景。该芯片的低功耗特性也非常令人关注，适合于需要延长电池寿命的便携设备。芯片CD40174BCN的详细参数 CD40174BCN的主要...

产品型号CD40174BCN的Datasheet PDF文件预览

October 1987

Revised July 1999

CD40174BC • CD40175BC

Hex D-Type Flip-Flop • Quad D-Type Flip-Flop

General Description

Features

The CD40174BC consists of six positive-edge triggered D-

type flip-flops; the true outputs from each flip-flop are exter-

nally available. The CD40175BC consists of four positive-

edge triggered D-type flip-flops; both the true and comple-

ment outputs from each flip-flop are externally available.

■ Wide supply voltage range: 3V to 15V

■ High noise immunity: 0.45 V_DD(typ.)

■ Low power TTL compatibility:

fan out of 2 driving 74L or 1 driving 74 LS

■ Equivalent to MC14174B, MC14175B

■ Equivalent to MM74C174, MM74C175

All flip-flops are controlled by a common clock and a com-

mon clear. Information at the D inputs meeting the set-up

time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. The clearing opera-

tion, enabled by a negative pulse at Clear input, clears all

Q outputs to logical “0” and Q s (CD40175BC only) to logi-

cal “1”.

All inputs are protected from static discharge by diode

clamps to V_DDand V_SS

Ordering Code:

Order Number Package Number

Package Description

CD40174BCM

CD40174BCN

CD40175BCM

CD40175BCN

M16A

N16E

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP and SOIC

CD40174B

CD40175B

Top View

DS005987

www.fairchildsemi.com

Truth Table

Inputs

Clock

Outputs

Clear

(Note 1)

↑

H = HIGH Level

L = LOW Level

X = Irrelevant

↑ = Transition from LOW-to-HIGH level

NC = No change

Note 1: Q for CD40175B only

www.fairchildsemi.com

Absolute Maximum Ratings(Note 2)

(Note 3)

Recommended Operating

Conditions ^{(Note 3)}

DC Supply Voltage (V_DD

Input Voltage (V_IN

)

−0.5V to +18V

−0.5V to V_DD+0.5V_DC

−65°C to +150°C

DC Supply Voltage (V_DD

Input Voltage (V_IN

Operating Temperature Range (T_A)

)

3V to 15 V_DC

0V to V_DDV_DC

−40°C to +85°C

)

Storage Temperature Range (T_S)

Power Dissipation (P_D)

Dual-In-Line

Note 2: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Characteristics” provide con-

ditions for actual device operation.

700 mW

500 mW

Small Outline

Lead Temperature (T_L)

(Soldering, 10 seconds)

260°C

Note 3: V = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

CD40174BC/CD40175BC

−40°C

+25°C

+85°C

Symbol

Parameter

Conditions

= 5V, V = V or V

Units

Min

Max

Min

Typ

Max

Min

Max

Quiescent Device

µA

Current

= 10V, V = V or V

= 15V, V = V or V

120

0.05

LOW Level

= 5V

0.05

Output Voltage

= 10V

= 15V

= 5V

HIGH Level

4.95

9.95

4.95

9.95

4.95

9.95

Output Voltage

= 10V

= 15V

14.95

LOW Level

= 5V, V = 0.5V or 4.5V

1.5

3.0

4.0

1.5

3.0

4.0

1.5

3.0

4.0

Input Voltage

= 10V, V = 1V or 9V

= 15V, V = 1.5V or 13.5V

HIGH Level

= 5V, V = 0.5V or 4.5V

3.5

7.0

3.5

7.0

3.5

7.0

Input Voltage

= 10V, V = 1V or 9V

= 15V, V = 1.5V or 13.5V

11.0

0.52

1.3

11.0

0.44

1.1

11.0

0.36

0.9

LOW Level Output

Current (Note 4)

= 5V, V = 0.4V

0.88

2.25

8.8

µA

= 10V, V = 0.5V

= 15V, V = 1.5V

3.6

3.0

2.4

HIGH Level Output

Current (Note 4)

= 5V, V = 4.6V

−0.52

−1.3

−3.6

−0.44 −0.88

−1.1 −2.25

−0.36

−0.9

−2.4

= 10V, V = 9.5V

= 15V, V = 13.5V

−3.0

−8.8

−5

Input Current

= 15V, V = 0V

−0.30

−10

−0.30

−1.0

−5

= 15V, V = 15V

0.30

1.0

Note 4: I

and I are tested one output at a time.

www.fairchildsemi.com

AC Electrical Characteristics (Note 5)

_A= 25°C, C_L= 50 pF, R_L= 200k and t = t = 20 ns, unless otherwise specified

Symbol

, t

Parameter

Conditions

Min

Typ

Max

Units

Propagation Delay Time to a

Logical “0” or Logical “1” from

Clock to Q or Q (CD40175 Only)

Propagation Delay Time to a

Logical “0” from Clear to Q

= 5V

190

300

110

PHL PLH

= 10V

= 15V

= 5V

180

300

110

PHL

= 10V

= 15V

= 5V

Propagation Delay Time to a Logical

“1” from Clear to Q (CD40175 Only)

230

400

150

120

100

PLH

= 10V

= 15V

= 5V

Time Prior to Clock Pulse that

Data must be Present

= 10V

= 15V

= 5V

Time after Clock Pulse that

Data Must be Held

−11

−4

= 10V

= 15V

= 5V

−3

, t

Transition Time

100

200

100

THL TLH

= 10V

= 15V

= 5V

, t

Minimum Clock Pulse Width

Minimum Clear Pulse Width

Maximum Clock Rise Time

Maximum Clock Fall Time

Maximum Clock Frequency

130

250

100

WH WL

= 10V

= 15V

= 5V

120

250

100

= 10V

= 15V

= 5V

5.0

µs

MHz

RCL

= 10V

= 15V

= 5V

fCL

= 10V

= 15V

= 5V

5.0

2.0

5.0

6.0

3.5

= 10V

= 15V

Input Capacitance

Power Dissipation

Clear Input

Other Input

5.0

130

7.5

Per Package (Note 6)

Note 5: AC Parameters are guaranteed by DC correlated testing.

Note 6: C determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application

note, AN-90.

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Switching Time Waveforms

= t = 20 ns

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

Package Number M16A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

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CD40174BCN产品参数

型号:	CD40174BCN
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Contact Manufacturer
零件包装代码：	DIP
包装说明：	DIP,
针数：	16
Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01
风险等级：	5.74
系列：	4000/14000/40000
JESD-30 代码：	R-PDIP-T16
长度：	19.305 mm
逻辑集成电路类型：	D FLIP-FLOP
位数：	6
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-55 °C
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装形状：	RECTANGULAR
封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
传播延迟（tpd）：	300 ns
认证状态：	Not Qualified
座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	15 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
温度等级：	MILITARY
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
触发器类型：	POSITIVE EDGE
宽度：	7.62 mm
最小 fmax：	6 MHz
Base Number Matches：	1

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产品型号CD40174BCN的概述

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