CD4053芯片引脚定义引脚图及功能IC贸易商引脚图技术参数-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第670页更新时间：2025-01-22 12:11:12

产品型号CD4053的概述

CD4053芯片概述 CD4053是一种多路复用器/解复用器，属于CMOS（互补金属氧化物半导体）系列。它由三路模拟开关组成，每路开关可以独立控制，适合于选择信号和数据线路的应用。该芯片通常用于选择性信号处理、音频调节、信号切换及其他需要切换多个信号源的电路。 CD4053的工作电压范围广泛，通常为3V到15V，适合于多种低功耗应用，尤其在移动设备中具有显著优势。它的设计采用了低漏电流特性，可以在低功耗的情况下保证良好的开关性能。 CD4053详细参数 CD4053的关键参数如下： - 工作电压范围：3V到15V - 通道配置：3路模拟开关 - 开关噪声：小于 0.5V（典型值） - 输入阻抗：高达 100 MΩ - 输出阻抗：低于 100 Ω - 最大输入电压：等于电源电压（VDD） - 工作温度范围：-55°C到125°C - 封装类型：标准DIP、SOIC等在实际应用中，CD4...

产品型号CD4053的Datasheet PDF文件预览

November 1983

Revised August 2000

CD4051BC • CD4052BC • CD4053BC

Single 8-Channel Analog Multiplexer/Demultiplexer •

Dual 4-Channel Analog Multiplexer/Demultiplexer •

Triple 2-Channel Analog Multiplexer/Demultiplexer

General Description

Features

■ Wide range of digital and analog signal levels:

The CD4051BC, CD4052BC, and CD4053BC analog mul-

tiplexers/demultiplexers are digitally controlled analog

switches having low “ON” impedance and very low “OFF”

leakage currents. Control of analog signals up to 15V_p-p

digital 3 – 15V, analog to 15V_p-p

■ Low “ON” resistance: 80Ω (typ.) over entire 15V_p-p

signal-input range for V_DD− V_EE= 15V

can be achieved by digital signal amplitudes of 3−15V. For

example, if V_DD= 5V, V_SS= 0V and V_EE= −5V, analog sig-

■ High “OFF” resistance:

channel leakage of ±10 pA (typ.) at V_DD− V_EE= 10V

nals from −5V to +5V can be controlled by digital inputs of

0−5V. The multiplexer circuits dissipate extremely low qui-

escent power over the full V_DD−V_SSand V_DD−V_EEsupply

■ Logic level conversion for digital addressing signals of

3 – 15V (V_DD− V_SS= 3 – 15V) to switch analog signals

voltage ranges, independent of the logic state of the control

signals. When a logical “1” is present at the inhibit input ter-

minal all channels are “OFF”.

to 15 V_p-p(V_DD− V_EE= 15V)

■ Matched switch characteristics:

∆R_ON= 5Ω (typ.) for V_DD− V_EE= 15V

CD4051BC is a single 8-channel multiplexer having three

binary control inputs. A, B, and C, and an inhibit input. The

three binary signals select 1 of 8 channels to be turned

“ON” and connect the input to the output.

■ Very low quiescent power dissipation under all

digital-control input and supply conditions:

1 µ W (typ.) at V_DD− V_SS= V_DD− V_EE= 10V

■ Binary address decoding on chip

CD4052BC is a differential 4-channel multiplexer having

two binary control inputs, A and B, and an inhibit input. The

two binary input signals select 1 or 4 pairs of channels to

be turned on and connect the differential analog inputs to

the differential outputs.

CD4053BC is a triple 2-channel multiplexer having three

separate digital control inputs, A, B, and C, and an inhibit

input. Each control input selects one of a pair of channels

which are connected in a single-pole double-throw configu-

ration.

Ordering Code:

Order Number Package Number

Package Description

CD4051BCM

CD4051BCSJ

CD4051BCMTC

CD4051BCN

CD4052BCM

CD4052BCSJ

CD4052BCN

CD4053BCM

CD4053BCSJ

CD4053BCN

M16A

M16D

MTC16

N16E

M16A

M16D

N16E

M16A

M16D

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS005662

www.fairchildsemi.com

Connection Diagrams

Pin Assignments for DIP and SOIC

CD4051BC

CD4052BC

CD4053BC

Truth Table

INPUT STATES

“ON” CHANNELS

INHIBIT

CD4051B CD4052B CD4053B

0X, 0Y

1X, 1Y

2X, 2Y

3X, 3Y

cx, bx, ax

cx, bx, ay

cx, by, ax

cx, by, ay

cy, bx, ax

cy, bx, ay

cy, by, ax

cy, by, ay

NONE

*Don’t Care condition.

www.fairchildsemi.com

Logic Diagrams

CD4051BC

CD4052BC

www.fairchildsemi.com

Logic Diagrams (Continued)

CD4053BC

www.fairchildsemi.com

Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

DC Supply Voltage (V_DD

)

−0.5 V_DCto +18 V_DC

Input Voltage (V_IN

)

−0.5 V_DCto V_DD+0.5 V_DC

DC Supply Voltage (V_DD

)

+5 V_DCto +15 V_DC

Storage Temperature

Range (T_S)

Input Voltage (V_IN

)

0V to V_DDV_DC

−65°C to +150°C

Operating Temperature Range (T_A)

CD4051BC/CD4052BC/CD4053BC

Power Dissipation (P_D)

Dual-In-Line

−40°C to +85°C

700 mW

500 mW

Note 1: “Absolute Maximum Ratings” are those values beyond which the

safety of the device cannot be guaranteed. Except for “Operating Tempera-

ture Range” they are not meant to imply that the devices should be oper-

ated at these limits. The Electrical Characteristics tables provide conditions

for actual device operation.

Small Outline

Lead Temperature (T_L)

(soldering, 10 seconds)

260°C

DC Electrical Characteristics (Note 2)

−40°C

Min Max

+25°

+85°C

Min Max

Symbol

Parameter

Conditions

Units

Min

Typ

Max

Control A, B, C and Inhibit

I_IN

Input Current

_DD= 15V,

_EE= 0V

−0.1

−5

−0.1

−10

−1.0

µA

_IN= 0V

_DD= 15V,

_IN= 15V

_DD= 5V

_DD= 10V

_DD= 15V

V_EE= 0V

−5

0.1

1.0

I_DD

Quiescent Device Current

150

300

600

µA

Signal Inputs (V_IS) and Outputs (V_OS

)

R_ON

“ON” Resistance (Peak

for V_EE≤ V_IS≤ V_DD

_L= 10 kΩ

_DD= 2.5V,

_EE= −2.5V

)

(any channel

selected)

850

330

210

270

120

1050

400

1200

520

Ω

or V_DD= 5V,

_EE= 0V

_DD= 5V,

_EE= −5V

or V_DD= 10V,

_EE= 0V

_DD= 7.5V,

_EE= −7.5V

240

300

or V_DD= 15V,

_EE= 0V

∆R_ON

∆ “ON” Resistance

Between Any Two

Channels

_L= 10 kΩ

_DD= 2.5V,

_EE= −2.5V

(any channel

selected)

or V_DD= 5V,

V_EE= 0V

V_DD= 5V

V_EE= −5V

or V_DD= 10V,

_EE= 0V

_DD= 7.5V,

_EE= −7.5V

or V_DD= 15V,

V_EE= 0V

“OFF” Channel Leakage

V_DD=7.5V,

V_EE=−7.5V

Current, any channel “OFF” O/I=±7.5V, I/O=0V

±50

±0.01

±0.08

±50

±500

“OFF” Channel Leakage

Current, all channels

“OFF” (Common

OUT/IN)

Inhibit = 7.5V CD4051

±200

±2000

V_DD= 7.5V,

V_EE= −7.5V,

D4052

±200

±0.04

±0.02

±200

±2000

O/I = 0V

I/O = ±7.5V

CD4053

Control Inputs A, B, C and Inhibit

www.fairchildsemi.com

DC Electrical Characteristics (Continued)

−40°C

+25°

+85°C

Symbol

V_IL

Parameter

Conditions

Units

Min

Max

Min

Typ

Max

Min

Max

LOW Level Input Voltage

_EE= V_SS

R_L= 1 kΩ to V_SS

I_IS<2 µA on all OFF Channels

_IS= V_DDthru 1 kΩ

_DD= 5V

1.5

3.0

4.0

1.5

3.0

4.0

1.5

3.0

4.0

_DD= 10V

_DD= 15V

_DD= 5

V_IH

HIGH Level Input Voltage

Input Current

3.5

_DD= 10

_DD= 15

I_IN

_DD= 15V,

_IN= 0V

_EE= 0V

−5

−0.1

−10

−0.1

−1.0

µA

_DD= 15V,

_IN= 15V

−5

0.1

1.0

Note 2: All voltages measured with respect to V_SSunless otherwise specified.

www.fairchildsemi.com

AC Electrical Characteristics (Note 3)

T_A= 25°C, t_r= t_f= 20 ns, unless otherwise specified.

Symbol

t_PZH,

t_PZL

Parameter

Conditions

V_DD

Min

Typ

Max

Units

Propagation Delay Time from

Inhibit to Signal Output

(channel turning on)

Propagation Delay Time from

Inhibit to Signal Output

(channel turning off)

Input Capacitance

Control input

_EE= V_SS= 0V

10V

15V

600

225

160

210

100

1200

450

320

420

200

150

_L= 1 kΩ

_L= 50 pF

t_PHZ,

t_PLZ

V_EE= V_SS= 0V

_L= 1 kΩ

10V

15V

_L= 50 pF

C_IN

7.5

Signal Input (IN/OUT)

Output Capacitance

(common OUT/IN)

CD4051

C_OUT

10V

CD4052

V_EE= V_SS= 0V

CD4053

C_IOS

C_PD

Feedthrough Capacitance

Power Dissipation Capacitance

CD4051

0.2

110

140

CD4052

CD4053

Signal Inputs (V_IS) and Outputs (V_OS

)

Sine Wave Response

(Distortion)

_L= 10 kΩ

_IS= 1 kHz

10V

0.04

_IS= 5 V_p-p

_EE= V_SI= 0V

Frequency Response, Channel

“ON” (Sine Wave Input)

_L= 1 kΩ, V_EE= 0V, V_IS= 5V_p-p

10V

MHz

20 log₁₀V_OS/V_IS= −3 dB

_L= 1 kΩ, V_EE= V_SS= 0V, V_IS= 5V_p-p

20 log₁₀V_OS/V_IS= −40 dB

R_L= 1 kΩ, V_EE= V_SS= 0V, V_IS(A) = 5V_p-p

Feedthrough, Channel “OFF”

Crosstalk Between Any Two

Channels (frequency at 40 dB) 20 log₁₀V_OS(B)/V_IS(A) = −40 dB (Note 4)

t_PHL

t_PLH

Propagation Delay Signal

Input to Signal Output

_EE= V_SS= 0V

_L= 50 pF

10V

15V

Control Inputs, A, B, C and Inhibit

Control Input to Signal

Crosstalk

_EE= V_SS= 0V, R_L= 10 kΩ at both ends

of channel.

10V

mV (peak)

Input Square Wave Amplitude = 10V

t_PHL,

t_PLH

Propagation Delay Time from

Address to Signal Output

(channels “ON” or “OFF”)

_EE= V_SS= 0V

500

180

120

1000

360

_L= 50 pF

10V

15V

240

Note 3: AC Parameters are guaranteed by DC correlated testing.

Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.

www.fairchildsemi.com

Special Considerations

In certain applications the external load-resistor current

switch must not exceed 0.6V at T_A≤ 25°C, or 0.4V at

_A> 25°C (calculated from R_ONvalues shown). No V_DD

may include both V_DDand signal-line components. To

avoid drawing V_DDcurrent when switch current flows into

IN/OUT pin, the voltage drop across the bidirectional

current will flow through R_Lif the switch current flows into

OUT/IN pin.

Typical Performance Characteristics

“ON” Resistance vs Signal

Voltage for T_A= 25°C

“ON” Resistance as a

Function of Temperature for

_DD− V_EE= 10V

“ON” Resistance as a

Function of Temperature for

_DD− V_EE= 15V

V_DD− V_EE= 5V

www.fairchildsemi.com

Switching Time Waveforms

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

CD4053相关文章

配单直通车

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

电子百科

产品导航

产品型号CD4053的概述

产品型号CD4053的Datasheet PDF文件预览

CD4053相关产品..

CD4053相关文章

IC37:专业IC行业平台