CDCLVP1204RGTR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第671页更新时间：2024-10-25 17:49:43

产品型号CDCLVP1204RGTR的概述

CDCLVP1204RGTR 芯片概述 CDCLVP1204RGTR是一款高性能的时钟分配器和缓冲器，广泛应用于高速数据传输和通信系统中的时钟管理领域。此芯片由德州仪器（Texas Instruments）公司设计制造，专为满足现代电子设备的高频时钟要求而设计。通过集成多个时钟输出和低相位噪声特性，CDCLVP1204RGTR能够在时钟信号的分配和处理上提供出色的性能，特别是在需要高频、低抖动信号的应用中。详细参数 CDCLVP1204RGTR的技术规格涵盖多个方面，包括但不限于以下几个主要参数： - 供电电压：芯片的工作电压范围通常为3.3V±10%。 - 输出频率范围：支持高达1.5GHz的输出频率，适合绝大多数的高速应用场景。 - 输出信号类型：该芯片提供多种输出信号，包括单端和差分信号。 - 相位噪声：CDCLVP1204RGTR的相位噪声表现较好，能够在一定频段内维持低噪声...

产品型号CDCLVP1204RGTR的Datasheet PDF文件预览

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

Four LVPECL Output,

High-Performance Clock Buffer

Check for Samples: CDCLVP1204

FEATURES

DESCRIPTION

The CDCLVP1204 is a highly versatile, low additive

jitter buffer that can generate four copies of LVPECL

clock outputs from one of two selectable LVPECL,

•

2:4 Differential Buffer

Selectable Clock Inputs Through Control Pin

Universal Inputs Accept LVPECL, LVDS, and

LVCMOS/LVTTL

LVDS, or LVCMOS inputs for

variety of

communication applications. It has a maximum clock

frequency up to 2 GHz. The CDCLVP1204 features

an on-chip multiplexer (MUX) for selecting one of two

inputs that can be easily configured solely through a

control pin. The overall additive jitter performance is

less than 0.1 ps, RMS from 10 kHz to 20 MHz, and

overall output skew is as low as 15 ps, making the

device a perfect choice for use in demanding

applications.

•

Four LVPECL Outputs

Maximum Clock Frequency: 2 GHz

Maximum Core Current Consumption: 45 mA

Very Low Additive Jitter: <100 fs,rms in 10-kHz

to 20-MHz Offset Range

•

2.375-V to 3.6-V Device Power Supply

Maximum Propagation Delay: 450 ps

Maximum Output Skew: 15 ps

The CDCLVP1204 clock buffer distributes one of two

selectable clock inputs (IN0, IN1) to four pairs of

differential LVPECL clock outputs (OUT0, OUT3) with

minimum skew for clock distribution. The

CDCLVP1204 can accept two clock sources into an

input multiplexer. The inputs can be LVPECL, LVDS,

or LVCMOS/LVTTL.

LVPECL Reference Voltage, V_{AC_REF}, Available

for Capacitive-Coupled Inputs

•

Industrial Temperature Range: –40°C to +85°C

ESD Protection Exceeds 2 kV (HBM)

Available in 3-mm × 3-mm QFN-16 (RGT)

Package

The CDCLVP1204 is specifically designed for driving

50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(V_{AC_REF}) should be applied to the unused negative

input pin. However, for high-speed performance up to

2 GHz, differential mode is strongly recommended.

APPLICATIONS

•

Wireless Communications

Telecommunications/Networking

Medical Imaging

The CDCLVP1204 is packaged in a small 16-pin,

3-mm x 3-mm QFN package and is characterized for

operation from –40°C to +85°C.

Test and Measurement Equipment

V_CC

INP0

INN0

INP1

INN1

OUTP[3...0]

LVPECL

OUTN[3...0]

IN_SEL

Reference

Generator

V_{AC_REF}

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTIONS⁽¹⁾

T_A

PACKAGED DEVICES

CDCLVP1204RGTT

CDCLVP1204RGTR

FEATURES

16-pin QFN (RGT) package, small tape and reel

16-pin QFN (RGT) package, tape and reel

–40°C to +85°C

(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or

refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted).⁽¹⁾

CDCLVP1204

–0.5 to 4.6

–0.5 to V_CC+0.5

UNIT

V_CC

V_IN

Supply voltage range⁽²⁾

(3)

Input voltage range

(3)

V_OUT

I_IN

I_OUT

T_A

Output voltage range

Input current

°C

Output current

Specified free-air temperature range (no airflow)

Storage temperature range

Maximum junction temperature

Electrostatic discharge (HBM)

–40 to +85

–65 to +150

+125

T_STG

T_J

ESD

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All supply voltages must be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).

CDCLVP1204

PARAMETER

Supply voltage

Ambient temperature

MIN

2.375

–40

TYP

MAX

3.60

+85

UNIT

V_CC

T_A

2.50/3.30

°C

PACKAGE DISSIPATION RATINGS^{(1) (2)}

VALUE

TEST

2 × 2 VIAS

PARAMETER

CONDITIONS

ON PAD

UNIT

0 LFM

51.8

22.6

19.2

6.12

°C/W

θ_JA

Thermal resistance, junction-to-ambient

Thermal resistance, junction-to-pad

150 LFM

400 LFM

(3)

θ_JP

(1) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(2) Connected to GND with four thermal vias (0.3-mm diameter).

(3) θ_JP(junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN

package.

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

ELECTRICAL CHARACTERISTICS: LVCMOS Input⁽¹⁾

At V_CC= 2.375 V to 3.6 V and T_A= –40°C to +85°C (unless otherwise noted).

CDCLVP1204

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN

Input frequency

200

MHz

External threshold voltage applied to

complementary input

V_th

Input threshold voltage

1.1

1.8

V_IH

Input high voltage

Input low voltage

Input high current

Input low current

Input edge rate

V_th+ 0.1

V_CC

_th– 0.1

V_IL

I_IH

V_CC= 3.6 V, V_IH= 3.6 V

V_CC= 3.6 V, V_IL= 0 V

20% to 80%

μA

V/ns

I_IL

–40

ΔV/ΔT

I_CAP

1.5

Input capacitance

(1) Figure 3 and Figure 4 show dc test setup.

ELECTRICAL CHARACTERISTICS: Differential Input⁽¹⁾

At V_CC= 2.375 V to 3.6 V and T_A= –40°C to +85°C (unless otherwise noted).

CDCLVP1204

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

2000

1.5

UNIT

MHz

f_IN

Input frequency

Clock input

f_IN≤ 1.5 GHz

0.1

0.2

1.0

V_{IN, DIFF, PP}

Differential input peak-peak voltage

1.5 GHz ≤ f_IN≤ 2 GHz

1.5

V_ICM

I_IH

Input common-mode level

Input high current

Input low current

_CC– 0.3

V_CC= 3.6 V, V_IH= 3.6 V

V_CC= 3.6 V, V_IL= 0 V

20% to 80%

μA

V/ns

I_IL

–40

ΔV/ΔT

I_CAP

Input edge rate

1.5

Input capacitance

(1) Figure 5 and Figure 6 show dc test setup. Figure 7 shows ac test setup.

ELECTRICAL CHARACTERISTICS: LVPECL Output⁽¹⁾

At V_CC= 2.375 V to 2.625 V and T_A= –40°C to +85°C (unless otherwise noted).

CDCLVP1204

TYP

PARAMETER

TEST CONDITIONS

MIN

_CC– 1.26

MAX

UNIT

V_OH

Output high voltage

_CC– 0.9

_CC– 1.3

1.35

V_OL

Output low voltage

V_CC– 1.7

V_{OUT, DIFF, PP}

V_{AC_REF}

Differential output peak-peak voltage

Input bias voltage⁽²⁾

f_IN≤ 2 GHz

0.5

I_{AC_REF}= 2 mA

V_{IN, DIFF, PP}= 0.1V

V_{IN, DIFF, PP}= 0.3V

V_CC– 1.6

_CC– 1.1

450

t_PD

Propagation delay

450

t_SK,PP

t_SK,O

Part-to-part skew

Output skew

100

Crossing-point-to-crossing-point distortion,

f_OUT= 100 MHz

t_SK,P

Pulse skew (with 50% duty cycle input)

–50

f_OUT= 100 MHz, V_IN,SE= V_CC, V_th= 1.25 V,

10 kHz to 20 MHz

0.081

0.091

0.041

0.088

ps, RMS

f_OUT= 100 MHz, V_IN,SE= 0.9 V,

V_th= 1.1 V, 10 kHz to 20 MHz

Random additive jitter (with 50% duty

cycle input)

f_OUT= 2 GHz, V_IN,DIFF,PP= 0.2 V,

V_ICM= 1 V, 10 kHz to 20 MHz

t_RJIT

f_OUT= 100 MHz, V_IN,DIFF,PP= 0.15 V,

V_ICM= 1 V, 10 kHz to 20 MHz

(1) Figure 8 and Figure 9 show dc and ac test setup.

(2) Internally generated bias voltage (V_{AC_REF}) is for 3.3-V operation only. It is recommended to apply externally generated bias voltage for

_CC< 3.0 V.

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

ELECTRICAL CHARACTERISTICS: LVPECL Output⁽¹⁾(continued)

At V_CC= 2.375 V to 2.625 V and T_A= –40°C to +85°C (unless otherwise noted).

CDCLVP1204

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

f_OUT= 100 MHz, V_IN,DIFF,PP= 1 V,

V_ICM= 1 V, 10 kHz to 20 MHz

0.081

ps, RMS

t_R/t_F

I_EE

Output rise/fall time

20% to 80%

200

Supply internal current

Outputs unterminated

I_CC

Output and internal supply current

All outputs terminated, 50 Ω to V_CC– 2

170

ELECTRICAL CHARACTERISTICS: LVPECL Output⁽¹⁾

At V_CC= 3.0 V to 3.6 V and T_A= –40°C to +85°C (unless otherwise noted).

CDCLVP1204

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

_CC– 0.9

_CC– 1.3

1.35

UNIT

V_OH

Output high voltage

_CC– 1.26

V_OL

Output low voltage

_CC– 1.7

V_{OUT, DIFF, PP}

V_{AC_REF}

Differential output peak-peak voltage

Input bias voltage

f_IN≤ 2 GHz

0.65

I_{AC_REF}= 2 mA

V_{IN, DIFF, PP}= 0.1V

V_{IN, DIFF, PP}= 0.3V

_CC– 1.6

V_CC– 1.1

450

t_PD

Propagation delay

450

t_SK,PP

t_SK,O

Part-to-part skew

Output skew

100

Crossing-point-to-crossing-point distortion,

f_OUT= 100 MHz

t_SK,P

Pulse skew (with 50% duty cycle input)

–50

f_OUT= 100 MHz, V_IN,SE= V_CC, V_th= 1.65 V,

10 kHz to 20 MHz

0.079

0.097

0.058

0.094

0.088

ps, RMS

f_OUT= 100 MHz, V_IN,SE= 0.9 V,

V_th= 1.1 V, 10 kHz to 20 MHz

Random additive jitter (with 50% duty

cycle input)

f_OUT= 2 GHz, V_IN,DIFF,PP= 0.2 V,

V_ICM= 1 V, 10 kHz to 20 MHz

t_RJIT

f_OUT= 100 MHz, V_IN,DIFF,PP= 0.15 V,

V_ICM= 1 V, 10 kHz to 20 MHz

f_OUT= 100 MHz, V_IN,DIFF,PP= 1 V,

V_ICM= 1 V, 10 kHz to 20 MHz

t_R/t_F

I_EE

Output rise/fall time

20% to 80%

200

Supply internal current

Outputs unterminated

I_CC

Output and internal supply current

All outputs terminated, 50 Ω to V_CC– 2

170

(1) Figure 8 and Figure 9 show dc and ac test setup.

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

RGT PACKAGE

QFN-16

(TOP VIEW)

V_{AC_REF}

OUTP2

OUTN2

OUTP3

OUTN3

CDCLVP1204

INN0

INP0

V_CC

Thermal Pad⁽¹⁾

(1) Thermal pad must be soldered to ground.

PIN DESCRIPTIONS

CDCLVP1204 Pin Descriptions

TERMINAL

NAME

TERMINAL

NO.

PULL-UP/

PULLDOWN

TYPE

Power

Ground

Input

DESCRIPTION

V_CC

GND

—

3.3-V supply for the device

Device ground

INP0, INN0

6, 7

Differential input pair or single-ended input. Unused input pair can be left floating.

Redundant differential input pair or single-ended input. Unused input pair can be

left floating.

INP1, INN1

3, 4

Input

—

OUTP3,

OUTN3

15, 16

13, 14

11, 12

9, 10

Output

Differential LVPECL output pair no. 3. Unused output pair can be left floating.

Differential LVPECL output pair no. 2. Unused output pair can be left floating.

Differential LVPECL output pair no. 1. Unused output pair can be left floating.

Differential LVPECL output pair no. 0. Unused output pair can be left floating.

OUTP2,

OUTN2

OUTP1,

OUTN1

OUTP0

OUTN0

Bias voltage output for capacitive-coupled inputs. Do not use V_{AC_REF}at V_CC

V_{AC_REF}

IN_SEL

—

3.0 V. If used, it is recommended to use a 0.1-μF capacitor to GND on this pin.

The output current is limited to 2 mA.

Pulldown

(see Table 1)

MUX select input for input choice (see Table 2)

Table 1. Pin Characteristics

PARAMETER

MIN

TYP

MAX

UNITS

R_PULLDOWN

Input pulldown resistor

150

kΩ

Table 2. Input Selection Table

IN_SEL

ACTIVE CLOCK INPUT

INP0, INN0

INP1, INN1

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

TYPICAL CHARACTERISTICS

At T_A= –40°C to +85°C (unless otherwise noted).

DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE

vs FREQUENCY

1.0

V_CC= 2.375 V

T_A= -40°C to +85°C

0.9

V_ICM= 1 V

V_IN,DIFF,PP= Min

0.8

0.7

0.6

0.5

0.4

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency (GHz)

Figure 1.

DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE

vs FREQUENCY

1.1

1.2

1.3

1.0

0.9

0.8

0.7

0.6

0.5

0.4

V_CC= 3.0 V

T_A= -40°C to +85°C

V_ICM= 1 V

V_IN,DIFF,PP= Min

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Frequency (GHz)

Figure 2.

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

TEST CONFIGURATIONS

This section describes the function of each block for the CDCLVP1204. Figure 3 through Figure 9 illustrate how

the device should be setup for a variety of test configurations.

V_IH

V_th

V_IL

V_th

Figure 3. DC-Coupled LVCMOS Input During Device Test

V_CC

V_IHmax

V_thmax

V_ILmax

V_IH

V_th

V_IL

V_IHmin

V_thmin

V_ILmin

GND

Figure 4. V_thVariation over LVCMOS Levels

V_CC

130 W

CDCLVP1204

LVPECL

82 W

Figure 5. DC-Coupled LVPECL Input During Device Test

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

100 W

CDCLVP1204

LVDS

Figure 6. DC-Coupled LVDS Input During Device Test

V_CC

82 W

CDCLVP1204

Differential

130 W

Figure 7. AC-Coupled Differential Input to Device

Oscilloscope

LVPECL

50 W

V_CC- 2 V

Figure 8. LVPECL Output DC Configuration During Device Test

Phase Noise

Analyzer

LVPECL

150 W

50 W

Figure 9. LVPECL Output AC Configuration During Device Test

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11.

V_OH

OUTNx

VOD

V_OL

OUTPx

80%

20%

0 V

V_OUT,DIFF,PP(= 2 ´ VOD)

t_R

t_F

Figure 10. Output Voltage and Rise/Fall Time

INNx

INPx

t_PLH0

OUTN0

OUTP0

t_PLH1

OUTN1

OUTP1

t_PLH2

OUTN2

OUTP2

t_PLH3

OUTN3

OUTP3

(1) Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn

(n = 0, 1, 2, 3), or as the difference between the fastest and the slowest t_PHLn(n = 0, 1, 2, 3).

(2) Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest

t_PLHn(n = 0, 1, 2, 3) across multiple devices, or the difference between the fastest and the slowest t_PHLn(n = 0, 1, 2,

3) across multiple devices.

Figure 11. Output and Part-to-Part Skew

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

APPLICATION INFORMATION

Thermal Management

Power consumption of the CDCLVP1204 can be high enough to require attention to thermal management. For

reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as

an estimate, ambient temperature (T_A) plus device power consumption times θ_JAshould not exceed +125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be

soldered down to ensure adequate heat conduction out of the package. Figure 12 shows a recommended land

and via pattern.

1,6 mm (min)

0,33 mm (typ)

0,5 mm (typ)

Figure 12. Recommended PCB Layout

Power-Supply Filtering

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter/phase noise is very critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system

against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required

by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,

they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It

is recommended to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply

pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply

and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these

beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with

very low dc resistance because it is imperative to provide adequate isolation between the board supply and the

chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required

for proper operation.

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

Figure 13 illustrates this recommended power-supply decoupling method.

V_CC

Board

Ferrite Bead

Supply

Chip

Supply

10 mF

1 mF

0.1 mF

Figure 13. Power-Supply Decoupling

LVPECL Output Termination

The CDCLVP1204 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are

required to ensure correct operation of the device and to minimize signal integrity. The proper termination for

LVPECL outputs is a 50 Ω to (V_CC–2) V, but this dc voltage is not readily available on PCB. Therefore, a

Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled

configurations. These configurations are shown in Figure 14a and b for V_CC= 2.5 V and Figure 15a and b for V_CC

= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the

receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required.

V_CC

250 W

CDCLVP1204

LVPECL

62.5 W

(a) Output DC Termination

V_BB

CDCLVP1204

LVPECL

86 W

50 W

(b) Output AC Termination

Figure 14. LVPECL Output DC and AC Termination for V_CC= 2.5 V

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

V_CC

130 W

CDCLVP1204

LVPECL

82 W

(a) Output DC Termination

V_BB

CDCLVP1204

LVPECL

150 W

50 W

(b) Output AC Termination

Figure 15. LVPECL Output DC and AC Termination for V_CC= 3.3 V

Input Termination

The CDCLVP1204 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 16 illustrates how

to dc couple an LVCMOS input to the CDCLVP1204. The series resistance (R_S) should be placed close to the

LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver

output impedance.

V_IH

V_th

V_IL

R_S

LVCMOS

CDCLVP1204

V_IH+ V_IL

V_th

Figure 16. DC-Coupled LVCMOS Input to CDCLVP1204

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

www.ti.com

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

Figure 17 shows how to dc couple LVDS inputs to the CDCLVP1204. Figure 18 and Figure 19 describe the

method of dc coupling LVPECL inputs to the CDCLVP1204 for V_CC= 2.5 V and V_CC= 3.3 V, respectively.

100 W

CDCLVP1204

LVDS

Figure 17. DC-Coupled LVDS Inputs to CDCLVP1204

V_CC

250 W

CDCLVP1204

LVPECL

62.5 W

Figure 18. DC-Coupled LVPECL Inputs to CDCLVP1204 (V_CC= 2.5 V)

V_CC

130 W

CDCLVP1204

LVPECL

82 W

Figure 19. DC-Coupled LVPECL Inputs to CDCLVP1204 (V_CC= 3.3 V)

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

CDCLVP1204

SCAS880C –AUGUST 2009–REVISED AUGUST 2011

www.ti.com

Figure 20 and Figure 21 show the technique of ac coupling differential inputs to the CDCLVP1204 for V_CC= 2.5

V and V_CC= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver

end or the receiver end. If the supply voltages of the driver and receiver are different, ac coupling is required.

V_CC

96 W

CDCLVP1204

Differential

105 W

Figure 20. AC-Coupled LVPECL Inputs to CDCLVP1204 (V_CC= 2.5 V)

V_CC

82 W

CDCLVP1204

Differential

130 W

Figure 21. AC-Coupled LVPECL Inputs to CDCLVP1204 (V_CC= 3.3 V)

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May, 2010) to Revision C

Page

•

Corrected V_ILparameter description in Electrical Characteristics table for LVCMOS inputs ............................................... 3

Added footnote (2) to Electrical Characteristics table for LVPECL Output, V_CC= 2.375 V to 2.625 V ................................ 3

Revised description of pin 8 .................................................................................................................................................. 5

Changed recommended resistor values in Figure 14(a) .................................................................................................... 11

Changed recommended resistor values in Figure 18 ......................................................................................................... 13

Changed recommended resistor values in Figure 19 ......................................................................................................... 13

Changes from Revision A (October, 2009) to Revision B

Page

•

Changed descriptions of INP0, INP1 and INN0, INN1 pins in Pin Descriptions table .......................................................... 5

Changed descriptions of all output pins in Pin Descriptions table ........................................................................................ 5

Submit Documentation Feedback

Product Folder Link(s): CDCLVP1204

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

CDCLVP1204RGTR

CDCLVP1204RGTT

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

QFN

RGT

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

1204

ACTIVE

RGT

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CDCLVP1204RGTR

CDCLVP1204RGTT

QFN

RGT

3000

250

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Feb-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCLVP1204RGTR

CDCLVP1204RGTT

QFN

RGT

3000

250

338.1

20.6

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

CDCLVP1204RGTR CDCLVP1204RGTT

CDCLVP1204RGTR相关文章

配单直通车

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

CDCLVP1204RGTR产品参数

型号:	CDCLVP1204RGTR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	QFN
包装说明：	QFN-16
针数：	16
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.27
Samacsys Confidence：	3
Samacsys Status：	Released
Samacsys PartID：	605459
Samacsys Pin Count：	17
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	RGT0016B-
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
系列：	CDC
输入调节：	MUX
JESD-30 代码：	S-PQCC-N16
JESD-609代码：	e4
长度：	3 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
湿度敏感等级：	2
功能数量：	1
反相输出次数：
端子数量：	16
实输出次数：	4
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	OPEN-EMITTER
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	2.5/3.3 V
最大电源电流（ICC）：	45 mA
Prop。Delay @ Nom-Sup：	0.45 ns
传播延迟（tpd）：	0.43 ns
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.015 ns
座面最大高度：	1 mm
子类别：	Clock Driver
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
最小 fmax：	2000 MHz
Base Number Matches：	1

电子百科

产品导航

产品型号CDCLVP1204RGTR的概述

产品型号CDCLVP1204RGTR的Datasheet PDF文件预览

CDCLVP1204RGTR相关产品

CDCLVP1204RGTR相关文章

IC37:专业IC行业平台