CDCU877AGQLR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>C字母起始型号索引_>C字母起始型号索引第664页更新时间：2024-10-25 17:24:23

产品型号CDCU877AGQLR的概述

引言随着电子技术的飞速发展，集成电路（IC）芯片在各个领域的应用越来越广泛。CDCU877AGQLR是一款功能强大的集成电路，主要用于信号处理和数据转换等应用领域。本文将对CDCU877AGQLR进行详细的概述和分析，包括其详细参数、厂商信息、封装形式、引脚配置、电路图说明以及实际应用案例。芯片概述 CDCU877AGQLR是一款高性能的类比数字转换器（ADC），特意设计用于在低功耗高性能的环境中工作。这款芯片的工作频率范围广泛，适用于许多应用，如音频处理、传感器输入以及数据采集系统。由于其优越的线性度和响应速度，CDCU877AGQLR在许多严苛的工业和消费电子设备中得到了广泛的应用。详细参数 CDCU877AGQLR的主要参数包括： - 输入电压范围：通常为0V至5V，能够适应多种信号源。 - 分辨率：12位，提供高精度的数据转换，适合细微变化的测量。 - 采样频率：支持高...

产品型号CDCU877AGQLR的Datasheet PDF文件预览

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌ ꢆꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

1.8-V Phase Lock Loop Clock Driver for

Double Data Rate (DDR II) Applications

External Feedback Pins (FBIN, FBIN) are

Used to Synchronize the Outputs to the

Input Clocks

Spread Spectrum Clock Compatible

Operating Frequency: 10 MHz to 400 MHz

Low Current Consumption: <135 mA

Low Jitter (Cycle-Cycle): 30 ps

Low Output Skew: 35 ps

Single-Ended Input and Single-Ended

Output Modes

Meets or Exceeds JESD82-8 PLL Standard

for PC2-3200/4300

Fail-Safe Inputs

Low Period Jitter: 20 ps

Low Dynamic Phase Offset:: 15 ps

Low Static Phase Offset:: 50 ps

Distributes One Differential Clock Input to

Ten Differential Outputs

52-Ball µBGA (MicroStar Junior BGA,

0,65-mm pitch) and 40-Pin MLF

description

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input

pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN),

the LVCMOS control pins (OE, OS), and the analog power input (AV ). When OE is low, the clock outputs, except

FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select)

is a program pin that must be tied to GND or V . When OS is high, OE functions as previously described. When

OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV

off and bypassed for test purposes.

is grounded, the PLL is turned

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit

on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state

where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being

differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock

between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C

to 85°C.

AVAILABLE OPTIONS

52-Ball BGA

40-Pin MLF

CDCU877ZQL

(Pb-Free)

−40°C to 85°C

CDCU877RTB

CDCU877AZQL

(Pb-Free)

CDCU877ARTB

−40°C to 85°C

CDCU877GQL

CDCU877AGQL

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior is a trademark of Texas Instruments.

ꢋ

ꢒ

ꢐ

ꢦ

ꢁ

ꢡ

ꢂ

ꢀ

ꢟ

ꢕ

ꢠ

ꢓ

ꢚ

ꢐ

ꢘ

ꢖ

ꢙ

ꢁ

ꢆ

ꢕ

ꢆ

ꢗ

ꢘ

ꢢ

ꢙ

ꢚ

ꢠ

ꢛ

ꢜ

ꢝ

ꢞ

ꢗ

ꢚ

ꢘ

ꢗ

ꢟ

ꢣ

ꢠ

ꢡ

ꢛ

ꢢ

ꢘ

ꢞ

ꢝ

ꢜ

ꢟ

ꢚ

ꢙ

ꢣ

ꢕꢢ

ꢡ

ꢤ

ꢟ

ꢥ

ꢗ

ꢠ

ꢝ

ꢟ

ꢞ

ꢗ

ꢞ

ꢚ

ꢛ

ꢘ

ꢡ

ꢦ

ꢝ

ꢘ

ꢞ

ꢢ

ꢟ

ꢈ

ꢛ

ꢚ

ꢠ

ꢞ

ꢚ

ꢛ

ꢜ

ꢞ

ꢚ

ꢟ

ꢣ

ꢗ

ꢙ

ꢗ

ꢠ

ꢢ

ꢛ

ꢞ

ꢧ

ꢞ

ꢢ

ꢛ

ꢚ

ꢙ

ꢨ

ꢝ

ꢓ

ꢘ

ꢜ

ꢢ

ꢟ

ꢞ

ꢝ

ꢘ

ꢦ

ꢝ

ꢛ

ꢦ

ꢩ

ꢝ

ꢞ ꢢ ꢟ ꢞꢗ ꢘꢫ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢈ

ꢛ

ꢝ

ꢘ

ꢞ

ꢪ

ꢈ

ꢋ

ꢛ

ꢚ

ꢦ

ꢡ

ꢠ

ꢞ

ꢗ

ꢚ

ꢘ

ꢣ

ꢛ

ꢚ

ꢠ

ꢢ

ꢟ

ꢗ

ꢘ

ꢫ

ꢦ

ꢚ

ꢢ

ꢟ

ꢘ

ꢚ

ꢞ

ꢘ

ꢢ

ꢠ

ꢢ

ꢟ

ꢝ

ꢛ

ꢗ

ꢥ

ꢪ

ꢗ

ꢘ

ꢠ

ꢥ

ꢡ

ꢦ

ꢢ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004



MicroStar Junior (GQL) Package

(TOP VIEW)

GND

DDQ

FBIN

DDQ

FBIN

DDQ

FBOUT

AGND

DDQ

FBOUT

GND

RTB PACKAGE

(TOP VIEW)

40 39 38 37 36 35 34 33 32 31

NC − No Connection

NB − No Ball

DDQ

FBIN

GND

FBOUT

DDQ

AGND

DDQ

GND

11 12 13 14 15 16 17 18 19 20

40-pin HP-VFQFP-N (6,0 x 6,0 mm Body Size,

0,5 mm Pitch, M0#220, Variation VJJD-2,

E2 = D2 = 2,9 mm 0,15 mm) Package Pinouts

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

Table 1. Terminal Functions

NAME

AGND

BGA

MLF

I/O

DESCRIPTION

Analog ground

Analog power

Clock input with a (10 kΩ to 100 kΩ) pulldown resistor

Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor

Feedback clock input

FBIN

FBOUT

Complementary feedback clock input

Feedback clock output

Complementary feedback clock output

Output enable (asynchronous)

Output select (tied to GND or V

)

GND

B2, B3, B4, B5,

C2, C5, H2, H5,

J2, J3, J4, J5

Ground

D2, D3, D4, E2,

E5, F2, G2, G3,

G4, G5

1, 6, 9, 15, 20,

23, 28, 31, 36

Logic and output power

Clock outputs

DDQ

Y[0:9]

A2, A1, D1, J1,

K3, A5, A6, D6,

J6, K4

38, 39, 3, 11, 14,

34, 33, 29, 19, 16

A3, B1, C1, K1,

K2, A4, B6, C6,

K6, K5

37, 40, 2, 12, 13,

35, 32, 30, 18, 17

Complementary clock outputs

Table 2. Function Table

INPUTS

OUTPUTS

FBOUT

PLL

FBOUT

Bypassed/

Off

GND

Bypassed/

Off

Bypassed/

Off

Bypassed/

Off

GND

Y7 Active

1.8 V Nominal

Y7 Active

1.8 V Nominal

Off

Reserved

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

Figure 1. Logic Diagram (Positive Logic)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

or AV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V

DDQ

Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

DDQ

Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

Input clamp current, I (V < 0 or V > V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

DDQ

Output clamp voltage, I

(V < 0 or V > V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

DDQ

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through each V

Storage temperature range, T

DDQ

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

DDQ

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

STG

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed

2. This value is limited to 2.5 V maximum.

recommended operating conditions

MIN NOM

MAX

UNIT

Output supply voltage

Supply voltage

1.7

1.8

1.9

DDQ

See Note 1

DDQ

Low-level input voltage (see Note 2) OE, OS

High-level input voltage (see Note 2) CK, CK

High-level output current (see Figure 2)

Low-level output current (see Figure 2)

Input differential-pair cross voltage

Input voltage level

0.35 × V

DDQ

0.65 × V

DDQ

−9

DDQ

/2)−0.15

−0.3

0.3

(V /2)+0.15

DDQ

+0.3

+0.4

Input differential voltage

(see Note 2 and Figure 9)

0.6

Operating free-air temperature

−40

°C

NOTES: 1. The PLL is turned off and bypassed for test purposes when AV

is grounded. During this test mode, V

recommended operating conditions and no timing parameters are ensured.

remains within the

DDQ

is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK

and CK V and V limits define the dc low and high levels for the logic detect state.

IH IL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

electrical characteristics over recommended operating free-air temperature range

DDQ

PARAMETER

Input (cl inputs)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I = 18 mA

1.7 V

−1.2

1.7 V to

1.9 V

DDQ

= −100 µA

− 0.2

High-level output voltage

= −9 mA

= 100 µA

= 9 mA

1.7 V

1.1

0.1

0.6

Low-level output voltage

1.7 V

1.9 V

Low-level output current, disabled

Differential output voltage (see Note 1)

CK, CK

= 100 mV, OE = L

100

0.5

µA

O(DL)

250

Input current

µA

OE, OS,

FBIN, FBIN

1.9 V

Supply current, static (I

+ I

)

CK and CK = L

500

DD(LD)

DDQ ADD

CK and CK = 270 MHz,

All outputs are open

(not connected to a PCB)

1.9 V

135

235

Supply current, dynamic (I )

(see Note 2 for C

+ I

calculation)

DDQ ADD

All outputs are loaded with 2 pF and

120-Ω termination resistor

CK, CK

V = V

or GND

1.8 V

Input capacitance

FBIN, FBIN

CK, CK

V = V

0.25

Change in input current

I(∆)

FBIN, FBIN

V = V

NOTES: 1. V

is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition.

2. Total I

= I

+ I

= f ×C ×V

, solving for C

= (I

+ I

)/(f

×V

) where f

is the input frequency, V

DD DDQ ADD CK PD DDQ

is the power supply, and C is the power dissipation capacitance.

PD DDQ ADD CK DDQ

DDQ

timing requirements over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

400

340

60%

UNIT

MHz

Clock frequency (operating, see Notes 1 and 2)

Clock frequency (application, see Notes 1 and 3)

Duty cycle, input clock

AV , V

DD DD

= 1.8 V 0.1 V

AV , V

DD DD

160

40%

AV , V

DD DD

Stabilization time (see Note 4)

AV , V

DD DD

µs

NOTES: 1. The PLL must be able to handle spread spectrum induced skew.

2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other

timing parameters (used for low speed system debug).

3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal

after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase

lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return

to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Note 1)

AV , V

= 1.8 V 0.1 V

DD DD

PARAMETER

TEST CONDITIONS

See Figure 11

MIN

TYP

MAX

UNIT

Enable time, OE to any Y/Y

Disable time, OE to any Y/Y

See Figure 11

dis

−40

−30

115

jit(cc+)

Cycle-to-cycle period jitter (see Note 8)

160 MHz to 190 MHz, see Figure 4

jit(cc−)

jit(cc+)

190 MHz to 340 MHz, see Figure 4

jit(cc−)

(ϕ)

Static phase offset time (see Note 2)

Dynamic phase offset time

Output clock skew

See Figure 5

−50

−15

See Figure 10

(ϕ)dyn

sk(o)

See Figure 6

160 MHz to 190 MHz, see Figure 7

190 MHz to 340 MHz, see Figure 7

160 MHz to 190 MHz, see Figure 8

190 MHz to 250 MHz, see Figure 8

250 MHz to 300 MHz, see Figure 8

300 MHz to 340 MHz, see Figure 8

See Figure 3 and Figure 9

−30

−20

−115

−70

−40

−60

0.5

Period jitter (see Notes 3 and 8)

jit(per)

Half-period jitter (see Notes 3 and 8)

jit(hper)

Slew rate, OE

V/ns

Input clock skew rate

2.5

Output clock slew rate

(see Notes 4 and 5)

See Figure 3 and Figure 9

See Figure 2, CDCU877

1.5

V/ns

/2)

− 0.1

/2)

+ 0.1

DDQ

Output differential-pair cross voltage

(see Note 6)

See Figure 2, CDCU877A (see Note 7)

(0−85°C)

DDQ

/2)

− 0.1

/2)

+ 0.1

DDQ

SSC modulation frequency

SSC clock input frequency deviation

PLL loop bandwidth

kHz

−0.5%

MHz

NOTES: 1. There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input

and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal

length cables must be used.

2. Phase static offset time does not include jitter.

3. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other.

4. The output slew rate is determined from the IBIS model into the load shown in Figure 3.

5. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and

feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended

target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the

requirements of the registered DDR2 DIMM application.

6. Output differential-pair cross voltage specified at the DRAM clock input or the test load.

of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application.

8. This parameter is assured by design and characterization.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

Figure 2. Output Load Test Circuit 1

Figure 3. Output Load Test Circuit 2

Figure 4. Cycle-To-Cycle Period Jitter

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

Figure 5. Static Phase Offset

Figure 6. Output Skew

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

Figure 7. Period Jitter

Figure 8. Half-Period Jitter

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

80%

V_ID, V_OD

20%

Clock Inputs

and Outputs, OE

t_r(i), t_r(o)

t_f(i), t_f(o)

V_80%V_20%

slrr_(i/o)

slrf_(i/o)=

t_r(i/o)

t_f(i/o)

Figure 9. Input and Output Slew Rates

Figure 10. Dynamic Phase Offset

Figure 11. Time Delay Between OE and Clock Output (Y, Y)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

RECOMMENDED AV

FILTERING

Bead

0603

CARD

VIA

AV _DD

V_DDQ

1 Ohm

0.1 uF

0603

4.7 uF

1206

2200 pF

0603

PLL

GND

AGND

CARD

VIA

See Notes 9, 10, and 11

Figure 12. Recommended AV

Filtering

NOTES: 9. Place the 2200-pF capacitor close to the PLL.

10. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND

via (farthest from the PLL).

11. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

MECHANICAL DATA

GQL (R-PBGA-N52)

PLASTIC BALL GRID ARRAY

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar Junior BGA configuration

D. Falls within JEDEC MO-225 variation BA.

E. This package is tin-lead (SnPb).

MicroStar Junior is a trademark of Texas Instruments.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢀꢂ ꢃ ꢄ ꢄꢅ ꢀ ꢁ ꢀꢂ ꢃꢄ ꢄ ꢆ

ꢇꢈ ꢃꢉꢊ ꢋꢌ ꢆ ꢍꢎ ꢏ ꢐꢀꢑ ꢏꢐ ꢐ ꢋ ꢀꢏ ꢐꢀ ꢑ ꢁꢒ ꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

MECHANICAL DATA

RTB (S-PQFP-N40)

PLASTIC QUAD FLATPACK

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. QFN (Quad Flatpack No-Lead) package configuration.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ

ꢇ ꢈꢃ ꢉꢊ ꢋꢌꢆ ꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐ ꢐꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ

ꢔ

SCAS688A − JUNE 2003 − REVISED JANUARY 2004

THERMAL PAD MECHANICAL DATA

PLASTIC QUAD FLATPACK

RTB (S−PQFP−N40)

Bottom View

Exposed Pad

3,05

2,75

3,05

2,75

Not to Scale

PPTD042

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. QFN (Quad Flatpack No−Lead) Package configuration.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

CDCU877AGQLR相关文章

配单直通车

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

柒号芯城电子商务（深圳）有限公司服务专线: 0755-83209937 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

CDCU877AGQLR产品参数

型号:	CDCU877AGQLR
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	BGA
包装说明：	VFBGA, BGA52,6X10,25
针数：	52
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	7.84
系列：	877
输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PBGA-B52
长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.009 A
功能数量：	1
反相输出次数：
端子数量：	52
实输出次数：	10
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA
封装等效代码：	BGA52,6X10,25
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.8 V
认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.035 ns
座面最大高度：	1 mm
子类别：	Clock Drivers
最大供电电压 (Vsup)：	1.9 V
最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	BALL
端子节距：	0.65 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.5 mm
最小 fmax：	340 MHz
Base Number Matches：	1

电子百科

产品导航

产品型号CDCU877AGQLR的概述

产品型号CDCU877AGQLR的Datasheet PDF文件预览

CDCU877AGQLR相关产品

CDCU877AGQLR相关文章

IC37:专业IC行业平台