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  • 万三科技(深圳)有限公司

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  • 数量6500000 
  • 厂家Texas Instruments(德州仪器) 
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  • 数量55000 
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  • 数量2015 
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  • 数量12500 
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  • CDCV850DGGR
  • 数量5800 
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  • CDCV850DGGR
  • 数量660000 
  • 厂家Texas Instruments(德州仪器) 
  • 封装48-TFSOP (0.240 
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  • 数量77225 
  • 厂家Texas Instruments 
  • 封装48-TFSOP(0.240,6.10mm 宽) 
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  • 厂家TI-德州仪器 
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  • 数量3685 
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  • 数量99000 
  • 厂家TI 
  • 封装TSSOP48 
  • 批号23+ 
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产品型号CDCV850DGGR的概述

CDCV850DGGR芯片概述 CDCV850DGGR是Texas Instruments(德州仪器)公司推出的一款高性能时钟缓冲器和时钟分配器。这款芯片特别适用于要求高度精确和低抖动时钟信号的应用,广泛用于通信设备、数据中心和高性能计算机系统。CDCV850DGGR不仅能够提供多个输出时钟信号,还支持多种输入频率,便于应用在不同的系统中。该芯片的设计确保在各种环境条件下都能保持稳定的性能,加之其低功耗特性,使其成为现代电子设计中的热门选择。 详细参数 以下是CDCV850DGGR的主要参数: 1. 工作电压:3.3V 2. 工作温度范围:-40°C至85°C 3. 输入频率范围:19MHz至200MHz 4. 输出时钟:支持多个输出,可进行分频 5. 功耗:最大功耗约为140mW 6. 抖动性能:典型总抖动为100ps 7. 封装类型:VQFN(虚焊盘塑料封装),16引脚 8. 封装...

产品型号CDCV850I的Datasheet PDF文件预览

ꢀꢁꢀ ꢂꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢇ  
ꢈ ꢉꢄ ꢊꢂ ꢋꢌꢍ ꢎꢏ ꢐ ꢑꢀ ꢒ ꢐ ꢑ ꢑꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢇ ꢂ ꢏꢓ  
ꢔ ꢇꢕ ꢌ ꢈ ꢊꢐ ꢇꢖꢏ ꢎꢏ ꢓꢇꢍ ꢐ ꢇꢖ ꢕꢏ ꢓꢗꢍ ꢀꢏ  
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
DGG PACKAGE  
(TOP VIEW)  
D
Phase-Lock Loop Clock Driver for Double  
Data-Rate Synchronous DRAM  
Applications  
GND  
Y0  
GND  
Y5  
1
48  
47  
46  
45  
44  
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
Operating Frequency: 60 to 140 MHz  
Low Jitter (cyc−cyc): 75 ps  
2
Y0  
Y5  
3
V
V
4
DDQ  
Y1  
DDQ  
Y6  
5
Distributes One Differential Clock Input to  
Ten Differential Outputs  
Y1  
GND  
GND  
Y2  
6
43 Y6  
7
42 GND  
41 GND  
40 Y7  
Two-Line Serial Interface Provides Output  
Enable and Functional Control  
8
9
Outputs Are Put Into a High-Impedance  
State When the Input Differential Clocks  
Are <20 MHz  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Y2  
Y7  
V
V
DDQ  
DDQ  
SCLK  
SDATA  
FBIN  
D
D
D
48-Pin TSSOP Package  
CLK  
CLK  
Consumes <250-µA Quiescent Current  
FBIN  
External Feedback Pins (FBIN, FBIN) Are  
Used to Synchronize the Outputs to the  
Input Clocks  
V
V
DDI  
DDQ  
AV  
FBOUT  
FBOUT  
GND  
Y8  
DD  
AGND  
GND  
Y3  
description  
Y3  
Y8  
The CDCV850 is a high-performance, low-skew,  
V
V
DDQ  
Y4  
DDQ  
low-jitter zero delay buffer that distributes a  
differential clock input pair (CLK, CLK) to ten  
differential pairs of clock outputs (Y[0:9], Y[0:9])  
and one differential pair of feedback clock outputs  
(FBOUT, FBOUT). The clock outputs are con-  
Y9  
Y4  
Y9  
GND  
GND  
trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,  
SCLK), and the analog power input (AV ). A two-line serial interface can put the individual output clock pairs  
DD  
in a high-impedance state. When the AV  
purposes.  
terminal is tied to GND, the PLL is turned off and bypassed for test  
DD  
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation  
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line  
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 k).  
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to  
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit  
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the  
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in  
applications where this programming option is not required (after power up, all output pairs will then be enabled).  
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),  
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low  
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.  
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.  
This stabilization time is required following power up, as well as changes to various 2-line serial registers that  
affect the PLL. The CDCV850 is characterized for both commercial and industrial temperature ranges.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢕꢤ  
Copyright 2002, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢉ  
1
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
TSSOP (DGG)  
CDCV850DGG  
CDCV850IDGG  
0°C to 85°C  
40°C to 85°C  
FUNCTION TABLE  
(Select Functions)  
OUTPUTS  
INPUTS  
PLL  
AV  
DD  
CLK  
L
CLK  
H
Y[0:9]  
Y[0:9]  
FBOUT  
FBOUT  
GND  
L
H
H
L
L
H
H
L
Bypassed/Off  
GND  
H
L
Bypassed/Off  
2.5 V (nom)  
2.5 V (nom)  
2.5 V (nom)  
L
H
L
H
L
H
On  
On  
Off  
H
L
H
L
H
L
<20 MHz <20 MHz  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Each output pair (except FBOUT, FBOUT) can be put into a high-impedance state through the 2-line  
serial interface.  
functional block diagram  
VDDI  
3
2
Y0  
Y0  
5
6
Y1  
Y1  
10  
9
Y2  
Y2  
12  
SCLK  
2-Line Serial  
Interface  
Logic  
10  
37  
20  
19  
SDATA  
Y3  
Y3  
22  
23  
Y4  
Y4  
46  
47  
Y5  
Y5  
13  
CLK  
44  
43  
Y6  
Y6  
14  
CLK  
PLL  
36  
FBIN  
39  
40  
Y7  
Y7  
35  
FBIN  
29  
30  
Y8  
Y8  
16  
AVDD  
27  
26  
Y9  
Y9  
32  
33  
FBOUT  
FBOUT  
2
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
Terminal Functions  
TERMINAL  
NAME  
AGND  
AV  
I/O  
DESCRIPTION  
NO.  
17  
Ground for 2.5-V analog supply  
2.5-V analog supply  
16  
DD  
CLK, CLK  
FBIN, FBIN  
FBOUT, FBOUT  
GND  
13, 14  
35, 36  
32, 33  
I
I
Differential clock input  
Feedback differential clock input  
Feedback differential clock output  
Ground  
O
1, 7, 8, 18,  
24, 25, 31,  
41, 42, 48  
SCLK  
12  
37  
I
Clock input for 2-line serial interface  
SDATA  
I/O Data input/output for 2-line serial interface  
2.5-V supply  
V
DDQ  
4, 11, 21,  
28, 34, 38,  
45  
V
DDI  
15  
I
2.5-V or 3.3-V supply for 2-line serial interface  
Y[0:9]  
Y[0:9]  
3, 5, 10,  
20, 22, 27,  
29, 39, 44,  
46  
O
Buffered output copies of input clock, CLK  
2, 6, 9, 19,  
23, 26, 30,  
40, 43, 47  
O
Buffered output copies of input clock, CLK  
3
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage range: V  
V
, AV  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V  
DDQ  
DDI  
DD  
Input voltage range: V (except SCLK and SDATA) (see Notes 1 and 2) . . . . . . . . 0.5 V to V  
+ 0.5 V  
+ 0.5 V  
+ 0.5 V  
+ 0.5 V  
I
DDQ  
V (SCLK, SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . 0.5 V to V  
I
DDI  
DDQ  
DDQ  
Output voltage range: V (except SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . 0.5 V to V  
O
V (SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
IK  
I
I
DDQ  
O
Output clamp current, I  
(V < 0 or V > V  
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
OK  
O
DDQ  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
O
O
DDQ  
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W  
JA  
stg  
Storage temperature range T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. This value is limited to 3.6 V maximum.  
3. The package thermal impedance is calculated in accordance with JESD 51.  
recommended operating conditions (see Note 4)  
MIN  
2.3  
TYP  
MAX  
UNIT  
V
V
, AV  
DD  
2.7  
3.6  
DDQ  
(see Note 5)  
Supply voltage  
V
2.3  
DDI  
CLK, CLK, HCSL Buffer only  
CLK, CLK  
0
0.24  
− 0.4  
−0.3  
V
DDQ  
Low level input voltage, V  
V
V
IL  
FBIN, FBIN  
V
/2 − 0.18  
DDQ  
SDATA, SCLK  
0.3 × V  
DDI  
CLK, CLK, HCSL Buffer only  
CLK, CLK  
0.66  
0.4  
0.71  
V
DDQ  
+ 0.3  
High level input voltage, V  
IH  
FBIN, FBIN  
V
/2 + 0.18  
DDQ  
SDATA, SCLK  
0.7 × V  
–0.3  
0.36  
0.2  
DDI  
DC input signal voltage (see Note 6)  
V
DDQ  
V
DDQ  
V
DDQ  
+ 0.3  
+ 0.6  
+ 0.6  
V
V
DC  
AC  
CLK, FBIN  
CLK, FBIN  
Differential input signal voltage, V (see Note 7)  
ID  
Input differential pair cross-voltage, V (see Note 8)  
IX  
0.45×(V −V  
)
0.55×(V −V  
)
V
IH IL  
IH IL  
High-level output current, I  
−12  
12  
mA  
V
OH  
Low-level output current, I  
OL  
SDATA  
3
mA  
V/ns  
kHz  
kHz  
Input slew rate, SR (see Figure 8)  
SSC modulation frequency  
1
30  
0
4
33.3  
−0.50  
85  
SSC clock input frequency deviation  
0
Commericial  
Industrial  
Operating free-air temperature, T  
°C  
A
−40  
85  
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.  
5. All devices on the serial interface bus, with input levels related to V  
, must have one common supply line to which the pullup resistor  
DDI  
is connected to.  
6. DC input signal voltage specifies the allowable dc execution of differential input.  
7. Differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level  
and VCP is the complementary input level.  
8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be  
crossing.  
4
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
= 2.3 V, I = 18 mA  
MIN  
TYP  
MAX  
UNIT  
V
V
Input voltage  
All inputs  
V
V
V
V
V
V
V
V
–1.2  
V
IK  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
I
= min to max, I  
= –1 mA  
= –12 mA  
V
DDQ  
– 0.1  
1.7  
OH  
High-level output voltage  
V
OH  
= 2.3 V,  
I
OH  
= min to max, I  
= 1 mA  
0.1  
0.6  
0.4  
OL  
Low-level output  
voltage  
SDATA  
= 2.3 V,  
= 3.0 V,  
I
I
= 12 mA  
= 3 mA  
= 1 V  
V
OL  
V
OL  
DDI  
OL  
I
I
High-level output current  
Low-level output current  
Output voltage swing  
= 2.3 V,  
= 2.3 V,  
V
V
–18  
26  
–32  
35  
mA  
mA  
V
OH  
DDQ  
DDQ  
O
= 1.2 V  
OL  
O
V
O
For load condition see Figure 3  
1.1  
V
DDQ  
– 0.4  
Output differential cross  
voltage  
V
OX  
V
DDQ  
/2 − 0.2  
V
DDQ  
/2  
V
DDQ  
/2 + 0.2  
V
SDATA,  
SCLK  
V
DDQ  
V
DDQ  
V
DDQ  
= 3.6 V,  
= 2.7 V,  
= 2.7 V,  
V = 0 V to 3.6 V  
+10/−50  
10  
µA  
µA  
µA  
I
I
I
I
Input current  
I
CLK, FBIN  
V = 0 V to 2.7 V  
I
High-impedance-state output  
current  
V
O
= V  
DDQ  
or GND  
10  
OZ  
Power-down current on V  
+ AV  
DD  
DDQ  
CLK at 0 MHz; Σ of I  
and AI  
DD  
150  
3
250  
20  
µA  
µA  
DD  
DDPD  
Power down current on V  
CLK at 0 MHz; V  
= 3.6 V  
f = 100 MHz  
O
DDI  
DDQ  
V
= 2.7 V,  
DDQ  
All differential output pairs are terminated  
with 120 / C = 4 pF  
I
Dynamic current on V  
DDQ  
205  
230  
mA  
DD  
L
AI  
(DD)  
Supply current on AV  
AV  
= 2.7 V,  
f = 100 MHz  
O
4
1
6
2
mA  
mA  
DD  
DD  
SCLK and  
SDATA = 3.6 V  
I
Supply current on V  
V
DDI  
= 3.6 V  
DDI  
DDI  
C
C
Input capacitance  
Output capacitance  
V
V
= 2.5 V  
= 2.5 V  
V = V  
DDQ  
or GND  
or GND  
2
2.5  
3
3
pF  
pF  
I
DDQ  
I
V = V  
O DDQ  
2.5  
3.5  
O
DDQ  
All typical values are at respective nominal V  
DDQ  
.
The value of V  
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-resistor, where VTR is the true input  
OC  
signal voltage and VCP is the complementary input signal voltage (see Figure 3).  
5
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature  
MIN  
60  
MAX  
140  
60%  
10  
UNIT  
f
Clock frequency  
MHz  
(CLK)  
Input clock duty cycle  
40%  
Stabilization time  
µs  
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a  
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,  
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under  
SSC application.  
timing requirements for the 2-line serial interface over recommended ranges of operating  
free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10)  
MIN  
MAX  
UNIT  
kHz  
µs  
f
t
t
t
t
SCLK frequency  
Bus free time  
100  
(SCLK)  
4.7  
4.7  
4.0  
4.7  
4.0  
(BUS)  
START setup time  
µs  
su(START)  
h(START)  
w(SCLL)  
START hold time  
µs  
SCLK low pulse duration  
µs  
t
t
t
t
t
t
SLCK high pulse duration  
SDATA input rise time  
SDATA input fall time  
SDATA setup time  
µs  
ns  
ns  
ns  
ns  
µs  
w(SCLH)  
r(SDATA)  
f(SDATA)  
su(SDATA)  
h(SDATA)  
su(STOP)  
1000  
300  
250  
0
SDATA hold time  
STOP setup time  
4
This conforms to I2C specification, version 2.1.  
6
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
switching characteristics over recommended ranges of operating free-air temperature (unless  
otherwisw noted)  
PARAMETER  
TEST CONDITIONS  
Test mode/CLK to any output  
SCLK to SDATA (acknowledge)  
Test mode/SDATA to Y-output  
Test mode/SDATA to Y-output  
100/133 MHz  
MIN  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
Propagation delay time  
4
pd  
{
High-to low-level propagation delay time  
Output enable time  
500  
ns  
PHL  
en  
85  
ns  
Output disable time  
35  
ns  
dis  
Jitter (period), See Figure 6  
Jitter (cycle-to-cycle), See Figure 3  
Half-period jitter, See Figure 7  
−30  
−30  
30  
30  
ps  
jit(per)  
jit(cc)  
jit(hper)  
100/133 MHz  
ps  
100/133 MHz  
−75  
75  
ps  
}
100 MHz/VID on CLK = 0.71 V  
100 MHz/VID on CLK = 0.59 V  
100 MHz/VID on CLK = 0.82 V  
133 MHz/VID on CLK = 0.71 V  
100 MHz/VID on CLK = 0.71 V  
100 MHz/VID on CLK = 0.59 V  
100 MHz/VID on CLK = 0.82 V  
133 MHz/VID on CLK = 0.71 V  
100 MHz/VID on CLK = 0.71 V  
133 MHz/VID on CLK = 0.71 V  
100 MHz/VID on CLK = 0.71 V  
133 MHz/VID on CLK = 0.71 V  
−120  
−50  
120  
160  
70  
w
W
W
}
w
W
W
}
}
}
}
0°C to 85°C  
ps  
ps  
−170  
−50  
180  
80  
t
Static phase offset, See Figure 4a  
()  
−160  
−90  
120  
30  
−40°C to 85°C  
−210  
−80  
150  
190  
140  
160  
130  
−190  
−140  
−160  
−130  
ps  
ps  
ps  
ps  
Dynamic phase offset, SSC on, See Figure 4b and  
Figure 9  
#
td  
()  
Dynamic phase offset, SSC off, See Figure 4b  
Output clock slew rate, terminated with 120  
/14 pF, See Figures 1 and 8  
t
1
1
2
3
V/ns  
V/ns  
slr(o)  
Output clock slew rate, terminated with 120  
/4 pF, See Figures 1 and 8  
t
t
slr(o)  
  
Output skew, See Figure 5  
75  
33.3  
ps  
kHz  
%
sk(o)  
SSC modulation frequency  
30  
SSC clock input frequency deviation  
0.00  
−0.50  
This time is for a PLL frequency of 100 MHz.  
§
#
||  
According CK00 spec: 6 x I at 50 and R = 475 Ω  
ref ref  
According CK00 spec: 5 x I at 50 and R = 475 Ω  
ref ref  
According CK00 spec: 7 x I at 50 and R = 475 Ω  
ref  
ref  
The parameter is assured by design but cannot be 100% production tested.  
All differential output pins are terminated with 120 /4 pF  
7
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
2-line serial interface  
2-line serial interface slave address  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
R/W  
1
1
0
1
0
0
1
0
Writing to the device is accomplished by sequentially sending the device address D2 , the dummy bytes  
H
(command code and the number of bytes), and the data bytes. This sequence is illustrated in the following  
tables:  
1 bit  
7 bits  
1 bit  
R/W  
1 bit  
Ack  
8 bits  
1 bit  
Ack  
8 bits  
Start Bit  
Slave Address  
Command Code  
Byte Count = N  
Ack  
Data Byte 0  
8 bits  
Ack  
1 bit  
Data Byte 1  
8 bits  
Ack  
Data Byte N  
8 bits  
Ack  
1 bit  
Stop  
1 bit  
1 bit  
1 bit  
2-line serial interface configuration command bitmap  
The 2-line serial command bytes are used to control the output clock pairs (Y[0:9], Y[0:9]). The output clock pairs  
are enabled after power up. During normal operation, the clock pairs can be disabled (set Hi-Z) or enabled  
(running) by writing the corresponding bit to the data bytes in the following tables:  
Byte 0: Enable/Disable Register  
(H = Enable, L = Disable)  
Byte 1: Enable/Disable Register  
(H = Enable, L = Disable)  
BIT  
PINS  
INITIAL  
VALUE  
DESCRIPTION  
BIT  
PINS  
INITIAL  
VALUE  
DESCRIPTION  
7
6
5
4
3
2
1
0
3, 2  
H
H
H
H
H
H
H
H
Y0, Y0  
Y1, Y1  
Y2, Y2  
Y3, Y3  
Y4, Y4  
Y5, Y5  
Y6, Y6  
Y7, Y7  
7
6
5
4
3
2
1
0
29, 30  
H
H
L
L
L
L
L
L
Y8, Y8  
5, 6  
27, 26  
Y9, Y9  
10, 9  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
20, 19  
22, 23  
46, 47  
44, 43  
39, 40  
8
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
V
DD  
V
(Y)  
R = 60 Ω  
R = 60 Ω  
V
DD  
/2  
V
(Y)  
CDCV850  
GND  
Figure 1. IBIS Model Output Load (used for slew rate measurement)  
V
DD  
/2  
C = 4 pF  
SCOPE  
CDCV850  
−V /2  
DD  
Z = 50 Ω  
Z = 60 Ω  
Z = 60 Ω  
R = 10 Ω  
R = 50 Ω  
GND  
R = 10 Ω  
Z = 50 Ω  
R = 50 Ω  
C = 4 pF  
GND  
−V /2  
DD  
−V /2  
DD  
Figure 2. Output Load Test Circuit  
Yx, FBOUT  
Yx, FBOUT  
t
t
c(n+1)  
c(n)  
t
= t  
− t  
jit(cc) c(n) c(n+1)  
Figure 3. Cycle-to-Cycle Jitter  
9
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
CLK  
CLK  
FBIN  
FBIN  
t
t
(
) n  
n = N  
1
(
) n+1  
t
(
) n  
t
(N is a large number of samples)  
=
)
(
N
(a) Static Phase Offset  
CLK  
CLK  
FBIN  
FBIN  
t
t
(
)
( )  
t
t
d(  
)
d( )  
t
t
d(  
)
d( )  
(b)  
Dynamic Phase Offset  
Figure 4. Static Phase Offset  
Yx  
Yx  
Yx, FBOUT  
Yx, FBOUT  
t
sk(o)  
Figure 5. Output Skew  
10  
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
Yx, FBOUT  
Yx, FBOUT  
t
c(n)  
Yx, FBOUT  
Yx, FBOUT  
1
f
O
1
t
= t −  
jit)per) c(n)  
f
O
Figure 6. Period Jitter  
Yx, FBOUT  
Yx, FBOUT  
t
t
(hper_N+1)  
(hper_n)  
1
f
O
1
t
= t  
jit(hper) (hper_n)  
2xf  
O
Figure 7. Half-Period Jitter  
11  
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
80%  
80%  
V , V  
ID OD  
20%  
20%  
Clock Inputs  
and Outputs  
t
, t  
slrf(i) slrf(o)  
t
, t  
slrr(i) slrr(o)  
Figure 8. Input and Output Slew Rates  
100  
99.9  
99.8  
99.7  
99.6  
99.5  
5
10  
15  
20  
25  
30  
35  
40  
45  
Period of Modulation Signal − µs  
Figure 9. SSC Modulation Profile  
12  
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
V
O
= 3.3 V  
R
= 1 kΩ  
L
DUT  
C
= 10 pF  
L
GND  
TEST CIRCUIT  
4 to N Bytes for Complete Device Programming  
Bit 0  
Start  
Condition  
(S)  
Stop  
Condition  
(P)  
Bit 7  
MSB  
Acknowledge  
(A)  
LSB  
Bit 6  
(R/W)  
t
t
su(START)  
t
w(SCLL)  
w(SCLH)  
0.7 V  
0.3 V  
CC  
SCLOCK  
CC  
t
t
r
su(START)  
t
PHL  
t
t
f
(BUS)  
t
PLH  
0.7 V  
0.3 V  
CC  
CC  
SDATA  
t
t
f(SDATA)  
t
r(SDATA)  
t
t
su(STOP)  
Stop Condition  
h(SDATA)  
Repeat Start  
t
su(SDATA)  
h(START)  
Condition  
(see Note A)  
Start or Repeat Start  
Condition  
VOLTAGE WAVEFORMS  
BYTE  
DESCRIPTION  
Slave Address  
1
2
3
Common (Dummy Value, Ignored)  
Byte Count = N  
4
Data Byte 0  
5 − N  
Data Byte 1 − N  
NOTE A: The repeat start condition is supported. If PWRDWN# is asserted SDATA will be set to off-state, high impedance.  
Figure 10. Propagation Delay Times, t and t  
r
f
13  
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SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002  
MECHANICAL DATA  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°ā8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: B. All linear dimensions are in millimeters.  
C. This drawing is subject to change without notice.  
D. Body dimensions do not include mold protrusion not to exceed 0,15.  
E. Falls within JEDEC MO-153  
14  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
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配单直通车
CDCV850DGGR产品参数
型号:CDCV850DGGR
Brand Name:Texas Instruments
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:TSSOP
包装说明:TSSOP, TSSOP48,.3,20
针数:48
Reach Compliance Code:compliant
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:5.77
系列:850
输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G48
JESD-609代码:e4
长度:12.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A
湿度敏感等级:2
功能数量:1
反相输出次数:
端子数量:48
实输出次数:10
最高工作温度:85 °C
最低工作温度:-40 °C
输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR
峰值回流温度(摄氏度):260
电源:2.5,2.5/3.3 V
传播延迟(tpd):4 ns
认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns
座面最大高度:1.2 mm
子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mm
最小 fmax:140 MHz
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