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  • CS4334K【原装现货】图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • CS4334K【原装现货】 现货库存
  • 数量86540 
  • 厂家CIRRUS 
  • 封装SOP-8 
  • 批号NEW 
  • █★特价全新原装现货
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    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • CS4334KS图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • CS4334KS 现货库存
  • 数量5000 
  • 厂家CS 
  • 封装SOP 
  • 批号2024+ 
  • 百分百原装正品,现货库存
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    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • CS4334KSZR图
  • 深圳市欧昇科技有限公司

     该会员已使用本站2年以上
  • CS4334KSZR 现货库存
  • 数量15900 
  • 厂家CIRRUS 
  • 封装SOP-8 
  • 批号19+ 
  • 原装原包新到货6A018现货
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  • -0755-83220848 QQ:2885528234
  • CS4334K图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • CS4334K 现货库存
  • 数量178 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • CS4334KSZ图
  • 深圳市羿芯诚电子有限公司

     该会员已使用本站7年以上
  • CS4334KSZ
  • 数量1000 
  • 厂家CIRRUS 
  • 封装SOP-8 
  • 批号21+ 
  • 羿芯诚只做原装 原厂渠道 价格优势
  • QQ:2881498351QQ:2881498351 复制
  • 0755-22968581 QQ:2881498351
  • CS4334K图
  • 深圳市宇川湘科技有限公司

     该会员已使用本站6年以上
  • CS4334K
  • 数量12660 
  • 厂家CRISTAL 
  • 封装SOP 
  • 批号23+ 
  • 原装正品现货,郑重承诺只做原装!
  • QQ:2885348305QQ:2885348305 复制
    QQ:2885348305QQ:2885348305 复制
  • 0755-84534256 QQ:2885348305QQ:2885348305
  • CS4334K图
  • 深圳市能元时代电子有限公司

     该会员已使用本站10年以上
  • CS4334K
  • 数量50000 
  • 厂家CS 
  • 封装SOP8 
  • 批号24+ 
  • 公司原装现货可含税!假一罚十!
  • QQ:2885637848QQ:2885637848 复制
    QQ:2885658492QQ:2885658492 复制
  • 0755-84502810 QQ:2885637848QQ:2885658492
  • CS4334KS图
  • 深圳市勤思达科技有限公司

     该会员已使用本站14年以上
  • CS4334KS
  • 数量150000 
  • 厂家CIRRUS 
  • 封装SOP-8 
  • 批号2019+ 
  • 全新原装,绝对正品,公司大量现货供应.
  • QQ:2881910282QQ:2881910282 复制
    QQ:2881239443QQ:2881239443 复制
  • 0755-83268779 QQ:2881910282QQ:2881239443
  • CS4334K图
  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • CS4334K
  • 数量5800 
  • 厂家CIRRUS 
  • 封装SOP 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
  • QQ:3003653665QQ:3003653665 复制
    QQ:1325513291QQ:1325513291 复制
  • 021-60341766 QQ:3003653665QQ:1325513291
  • CS4334K图
  • 深圳市赛尔通科技有限公司

     该会员已使用本站12年以上
  • CS4334K
  • 数量12850 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号NEW 
  • 绝对进口原装现货,市场价格最低!!
  • QQ:1134344845QQ:1134344845 复制
    QQ:847984313QQ:847984313 复制
  • 86-0755-83536093 QQ:1134344845QQ:847984313
  • CS4334K图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • CS4334K
  • 数量1000 
  • 厂家CS 
  • 封装QFP 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
  • QQ:800888908QQ:800888908 复制
  • 755-83950019 QQ:800888908
  • CS4334KSR图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • CS4334KSR
  • 数量5000 
  • 厂家CS 
  • 封装SO-8 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62104931 QQ:857273081QQ:1594462451
  • CS4334K图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • CS4334K
  • 数量1813 
  • 厂家CS 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
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    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • CS4334K图
  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • CS4334K
  • 数量8560 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号17+ 
  • 受权代理!全新原装现货特价热卖!
  • QQ:1258645397QQ:1258645397 复制
    QQ:876098337QQ:876098337 复制
  • 0755-83238902 QQ:1258645397QQ:876098337
  • CS4334KS图
  • 深圳市欧昇科技有限公司

     该会员已使用本站10年以上
  • CS4334KS
  • 数量9000 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号2021+ 
  • 港瑞电子是实报/实单可以来谈价
  • QQ:2885514621QQ:2885514621 复制
    QQ:1017582752QQ:1017582752 复制
  • 0755-83237676 QQ:2885514621QQ:1017582752
  • CS4334K图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CS4334K
  • 数量68002 
  • 厂家CIRRUS 
  • 封装SOP8 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
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    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • CS4334K图
  • 集好芯城

     该会员已使用本站13年以上
  • CS4334K
  • 数量16640 
  • 厂家CS 
  • 封装SOP 
  • 批号最新批次 
  • 原装原厂 现货现卖
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    QQ:3008092965QQ:3008092965 复制
  • 0755-83239307 QQ:3008092965QQ:3008092965
  • CS4334K图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CS4334K
  • 数量18300 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • CS4334KS图
  • 深圳市芳益电子科技有限公司

     该会员已使用本站10年以上
  • CS4334KS
  • 数量34889 
  • 厂家CRYSTAL 
  • 封装 
  • 批号2023+ 
  • 原装现货库存 低价出售 欢迎加Q详谈 诚信经营 可长期合作
  • QQ:498361569QQ:498361569 复制
    QQ:389337416QQ:389337416 复制
  • 0755-13631573466 QQ:498361569QQ:389337416
  • CS4334K图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • CS4334K
  • 数量2500 
  • 厂家CS 
  • 封装SOP8 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507165QQ:2355507165 复制
    QQ:2355507162QQ:2355507162 复制
  • 86-0755-83210909 QQ:2355507165QQ:2355507162
  • CS4334K图
  • 深圳市金嘉锐电子有限公司

     该会员已使用本站14年以上
  • CS4334K
  • 数量16000 
  • 厂家N/A 
  • 封装SOP3.9mm 
  • 批号24+ 
  • 【原装优势★★★绝对有货】 
  • QQ:2643490444QQ:2643490444 复制
  • 0755-22929859 QQ:2643490444
  • CS4334K图
  • 上海金庆电子技术有限公司

     该会员已使用本站15年以上
  • CS4334K
  • 数量2601 
  • 厂家CIRRUS LOGIC 
  • 封装SOP 
  • 批号新 
  • 全新原装 货期两周
  • QQ:1484215649QQ:1484215649 复制
    QQ:729272152QQ:729272152 复制
  • 021-51872561 QQ:1484215649QQ:729272152
  • CS4334KSZ图
  • 深圳市宇集芯电子有限公司

     该会员已使用本站6年以上
  • CS4334KSZ
  • 数量99000 
  • 厂家CIRRUS 
  • 封装SOP8 
  • 批号23+ 
  • 一级代理进口原装现货、假一罚十价格合理
  • QQ:1157099927QQ:1157099927 复制
    QQ:2039672975QQ:2039672975 复制
  • 0755-2870-8773手机微信同号13430772257 QQ:1157099927QQ:2039672975
  • CS4334K图
  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • CS4334K
  • 数量18926 
  • 厂家CRYSTRL 
  • 封装SOP 
  • 批号2020+ 
  • 全新原装进口现货特价热卖,长期供货
  • QQ:1327510916QQ:1327510916 复制
    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • CS4334K图
  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • CS4334K
  • 数量3565 
  • 厂家CIRRUSLOGIC 
  • 封装SOP8 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894392QQ:2881894392 复制
    QQ:2881894393QQ:2881894393 复制
  • 0755- QQ:2881894392QQ:2881894393
  • CS4334KS图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • CS4334KS
  • 数量15830 
  • 厂家CS 
  • 封装SOP 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • CS4334K   SOP图
  • 北京元坤伟业科技有限公司

     该会员已使用本站17年以上
  • CS4334K SOP
  • 数量5000 
  • 厂家
  • 封装SOPDIP 
  • 批号16+ 
  • 百分百原装正品,现货库存
  • QQ:857273081QQ:857273081 复制
    QQ:1594462451QQ:1594462451 复制
  • 010-62106431 QQ:857273081QQ:1594462451
  • CS4334K图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • CS4334K
  • 数量36500 
  • 厂家CRYSTRL 
  • 封装SOP 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
  • QQ:198857245QQ:198857245 复制
  • 0755-82865294 QQ:198857245
  • CS4334K图
  • 深圳市捷兴胜微电子科技有限公司

     该会员已使用本站13年以上
  • CS4334K
  • 数量420 
  • 厂家CS 
  • 封装SOP8 
  • 批号05+ 
  • 原装现货 专业集成电路,二三极管供应商
  • QQ:838417624QQ:838417624 复制
    QQ:929605236QQ:929605236 复制
  • 0755-23997656(现货库存配套一站采购及BOM优化) QQ:838417624QQ:929605236
  • CS4334K图
  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
  • CS4334K
  • 数量26800 
  • 厂家CRYSTAL 
  • 封装SOP8 
  • 批号22+ 
  • 授权代理直销,原厂原装现货,假一罚十,特价销售
  • QQ:287673858QQ:287673858 复制
  • 0755-82533534 QQ:287673858
  • CS4334K图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • CS4334K
  • 数量85000 
  • 厂家CLRRUS 
  • 封装19 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • CS4334KSZ                              P/b图
  • 北京中其伟业科技有限公司

     该会员已使用本站16年以上
  • CS4334KSZ P/b
  • 数量9210 
  • 厂家CS 
  • 封装SO-8 
  • 批号16+ 
  • 特价,原装正品,绝对公司现货库存,原装特价!
  • QQ:2880824479QQ:2880824479 复制
  • 010-62104891 QQ:2880824479
  • CS4334KS图
  • 深圳市西昂特科技有限公司

     该会员已使用本站13年以上
  • CS4334KS
  • 数量6000 
  • 厂家CRYSTAL 
  • 封装SOP 
  • 批号2010+ 
  • 全新原装现货特价
  • QQ:2881291855QQ:2881291855 复制
    QQ:1158574719QQ:1158574719 复制
  • 0755-82524647 QQ:2881291855QQ:1158574719
  • CS4334K图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • CS4334K
  • 数量13050 
  • 厂家CS 
  • 封装SOP 
  • 批号2023+ 
  • 绝对原装正品现货/优势渠道商、原盘原包原盒
  • QQ:1002316308QQ:1002316308 复制
    QQ:515102657QQ:515102657 复制
  • 深圳分公司0755-83777708“进口原装正品专供” QQ:1002316308QQ:515102657
  • CS4334KZ图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • CS4334KZ
  • 数量18000 
  • 厂家CIRRUS 
  • 封装SOP8 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • CS4334K/图
  • 北京首天国际有限公司

     该会员已使用本站16年以上
  • CS4334K/
  • 数量8880 
  • 厂家IC 
  • 封装SOP 
  • 批号2024+ 
  • 百分百原装正品,现货库存
  • QQ:528164397QQ:528164397 复制
    QQ:1318502189QQ:1318502189 复制
  • 010-62565447 QQ:528164397QQ:1318502189
  • CS4334KS图
  • 北京力通科信电子有限公司

     该会员已使用本站10年以上
  • CS4334KS
  • 数量3377 
  • 厂家crystal 
  • 封装vpe: 100/tube/smd 
  • 批号dc99 
  • 7-10天原装特价*热卖
  • QQ:2355365902QQ:2355365902 复制
    QQ:2355365899QQ:2355365899 复制
  • 010-82625766 QQ:2355365902QQ:2355365899

产品型号CS4334K的概述

芯片CS4334K的概述 CS4334K是美国Cirrus Logic公司推出的一款高性能数模转换器(DAC)。该芯片主要用于音频应用,由于其优异的音频性能,广泛应用于数字音频播放器、音响系统及其他音频处理设备。CS4334K具有高精度、高动态范围和低失真的特性,能够满足高保真音频的需求。同时,该DAC采用新型的Delta-Sigma转换架构,具有较宽的采样率范围和灵活的数字接口。 芯片CS4334K的详细参数 CS4334K的主要参数包括: 1. 采样率:支持的采样率为32kHz至192kHz,这使得该DAC能够兼容高分辨率音频格式。 2. 分辨率:提供高达24位分辨率的输出精度,能够还原更多的音频细节。 3. 动态范围:动态范围高达114 dB(A加权),使其在处理音频信号时能够保持出色的信噪比。 4. 失真:总谐波失真(THD+N)极低,通常小于-90 dB,适...

产品型号CS4334_04的Datasheet PDF文件预览

CS4334/5/8/9  
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter  
Features  
Description  
The CS4334 family members are complete, stereo  
Complete Stereo DAC System: Interpolation,  
D/A, Output Analog Filtering  
digital-to-analog output systems including interpolation,  
1-bit D/A conversion and output analog filtering in an  
8-pin package. The CS4334/5/8/9 support all major  
audio data interface formats, and the individual devices  
differ only in the supported interface format.  
24-Bit Conversion  
96 dB Dynamic Range  
The CS4334 family is based on Delta-Sigma modulation,  
where the modulator output controls the reference volt-  
age input to an ultra-linear analog low-pass filter. This  
architecture allows for infinite adjustment of sample rate  
between 2 kHz and 100 kHz simply by changing the  
master clock frequency.  
-88 dB THD+N  
Low Clock Jitter Sensitivity  
Single +5 V Power Supply  
Filtered Line Level Outputs  
On-Chip Digital De-emphasis  
Popguard® Technology  
Functionally Compatible with CS4330/31/33  
The CS4334 family contains on-chip digital de-empha-  
sis, operates from a single +5V power supply, and  
requires minimal support circuitry. These features are  
ideal for set-top boxes, DVD players, SVCD players, and  
A/V receivers.  
ORDERING INFORMATION  
See page 24  
I
DEM/SCLK  
2
AGND  
6
VA  
7
3
LRCK  
Serial Input  
De-emphasis  
Interface  
Voltage Reference  
1
SDATA  
Analog  
Low-Pass  
Filter  
∆Σ  
Interpolator  
AOUTL  
AOUTR  
DAC  
DAC  
Modulator  
8
5
Analog  
Low-Pass  
Filter  
∆Σ  
Interpolator  
Modulator  
4
MCLK  
Cirrus Logic, Inc.  
http://www.cirrus.com  
Copyright Cirrus Logic, Inc. 2004  
(All Rights Reserved)  
JUL ‘04  
DS248F3  
1
CS4334/5/8/9  
TABLE OF CONTENTS  
1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4  
SPECIFIED OPERATING CONDITIONS ................................................................................. 4  
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4  
ANALOG CHARACTERISTICS................................................................................................ 5  
POWER AND THERMAL CHARACTERISTICS....................................................................... 7  
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 8  
SWITCHING CHARACTERISTICS .......................................................................................... 9  
2. TYPICAL CONNECTION DIAGRAM ..................................................................................... 11  
3. GENERAL DESCRIPTION .................................................................................................... 12  
3.1 Digital Interpolation Filter ................................................................................................. 12  
3.2 Delta-Sigma Modulator .................................................................................................... 12  
3.3 Switched-Capacitor DAC ................................................................................................. 12  
3.4 Analog Low-Pass Filter .................................................................................................... 12  
4. SYSTEM DESIGN .................................................................................................................. 13  
4.1 Master Clock .................................................................................................................... 13  
4.2 Serial Clock ...................................................................................................................... 13  
4.2.1 External Serial Clock Mode ................................................................................. 13  
4.2.2 Internal Serial Clock Mode .................................................................................. 13  
4.3 De-Emphasis ................................................................................................................... 13  
4.4 Initialization and Power-Down .......................................................................................... 14  
4.5 Output Transient Control ..................................................................................................14  
4.6 Grounding and Power Supply Decoupling ....................................................................... 14  
4.7 Analog Output and Filtering ............................................................................................. 14  
4.8 Overall Base-Rate Frequency Response ........................................................................ 18  
4.9 Overall High-Rate Frequency Response ......................................................................... 19  
4.10 Base Rate Mode Performance Plots .............................................................................. 20  
Contacting Cirrus Logic Support  
For all product questions and inquiries contact a Cirrus Logic Sales Representative.  
To find one nearest you go to http://www.cirrus.com/  
IMPORTANT NOTICE  
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the infor-  
mation is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain  
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sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringe-  
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to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.  
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2
DS248F3  
CS4334/5/8/9  
4.11 High Rate Mode Performance Plots .............................................................................. 21  
5. PIN DESCRIPTIONS ............................................................................................................. 22  
6. PARAMETER DEFINITIONS ................................................................................................. 23  
7. REFERENCES ....................................................................................................................... 23  
8. ORDERING INFORMATION: ............................................................................................... 24  
9. FUNCTIONAL COMPATIBILITY ........................................................................................... 24  
10. PACKAGE DIMENSIONS ................................................................................................... 25  
LIST OF FIGURES  
Figure 1. Output Test Load .......................................................................................................... 7  
Figure 2. Maximum Loading......................................................................................................... 7  
Figure 3. Power vs. Sample Rate ................................................................................................ 7  
Figure 4. External Serial Mode Input Timing.............................................................................. 10  
Figure 5. Internal Serial Mode Input Timing............................................................................... 10  
Figure 6. Internal Serial Clock Generation................................................................................ 10  
Figure 7. Recommended Connection Diagram.......................................................................... 11  
Figure 8. System Block Diagram................................................................................................ 12  
Figure 9. De-Emphasis Curve (Fs = 44.1kHz) ........................................................................... 13  
2
Figure 10. CS4334 Data Format (I S).......................................................................................... 15  
Figure 11. CS4335 Data Format.................................................................................................. 15  
Figure 12. CS4338 Data Format.................................................................................................. 15  
Figure 13. CS4339 Data Format.................................................................................................. 16  
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence ............................................ 17  
Figure 15. Stopband Rejection..................................................................................................... 18  
Figure 16. Transition Band........................................................................................................... 18  
Figure 17. Transition Band........................................................................................................... 18  
Figure 18. Passband Ripple......................................................................................................... 18  
Figure 19. Stopband Rejection..................................................................................................... 19  
Figure 20. Transition Band........................................................................................................... 19  
Figure 21. Transition Band........................................................................................................... 19  
Figure 22. Passband Ripple......................................................................................................... 19  
Figure 23. 0 dBFS FFT (BRM)..................................................................................................... 20  
Figure 24. -60 dBFS FFT (BRM).................................................................................................. 20  
Figure 25. Idle Channel Noise FFT (BRM)................................................................................... 20  
Figure 26. Twin Tone IMD FFT (BRM)......................................................................................... 20  
Figure 27. THD+N vs. Amplitude (BRM)...................................................................................... 20  
Figure 28. THD+N vs. Frequency (BRM)..................................................................................... 20  
Figure 29. 0 dBFS FFT (HRM)..................................................................................................... 21  
Figure 30. -60 dBFS FFT (HRM).................................................................................................. 21  
Figure 31. Idle Channel Noise FFT (HRM) .................................................................................. 21  
Figure 32. Twin Tone IMD FFT (HRM) ........................................................................................ 21  
Figure 33. THD+N vs. Amplitude (HRM)...................................................................................... 21  
Figure 34. THD+N vs. Frequency (HRM)..................................................................................... 21  
Figure 35.  
LIST OF TABLES  
Table 1.  
Table 2.  
Common Clock Frequencies ..................................................................................... 13  
DS248F3  
3
CS4334/5/8/9  
1. CHARACTERISTICS AND SPECIFICATIONS  
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical  
performance characteristics and specifications are derived from measurements taken at nominal supply voltages  
and T = 25°C.)  
A
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)  
Parameters  
Symbol  
Min  
Nom  
Max  
Units  
DC Power Supply  
Ambient Operating Temperature (Power Applied)  
VA  
4.75  
5.0  
5.5  
V
-KS  
-BS/-DS  
-10  
-40  
-
-
+70  
+85  
°C  
°C  
T
A
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)  
Parameters  
Symbol  
Min  
-0.3  
-
Max  
Units  
V
DC Power Supply  
VA  
6.0  
Input Current, Any Pin Except Supplies  
Digital Input Voltage  
I
10  
mA  
V
in  
V
-0.3  
-55  
-65  
VA+0.4  
125  
IND  
Ambient Operating Temperature (power applied)  
Storage Temperature  
T
°C  
A
T
150  
°C  
stg  
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is  
not guaranteed at these extremes.  
4
DS248F3  
CS4334/5/8/9  
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R = 10 k, C =  
L
L
10 pF (see Figure 1). Fs for Base-Rate Mode = 48 kHz, Measurement Bandwidth 10 Hz to 20 kHz, unless other-  
wise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise spec-  
ified.)  
Base-Rate Mode  
High-Rate Mode  
Parameter  
Symbol Min  
Typ  
Max Min  
Typ  
Max Unit  
Dynamic Performance for CS4334/5/8/9-KS  
Dynamic Range  
(Note 1)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
18 to 24-Bit  
16-Bit  
88  
91  
86  
89  
93  
96  
91  
94  
-
-
-
-
-
91  
-
90  
96  
88  
94  
-
-
-
-
dB  
dB  
dB  
dB  
89  
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 1) THD+N  
0 dB  
-20 dB  
-60 dB  
0 dB  
-20 dB  
-60 dB  
-
-
-
-
-
-
-88  
-73  
-33  
-86  
-71  
-31  
-83  
-68  
-28  
-81  
-66  
-26  
-
-
-
-
-
-
-88  
-70  
-30  
-86  
-68  
-28  
-83  
-65  
-25  
-81  
-63  
-23  
dB  
dB  
dB  
dB  
dB  
dB  
16-Bit  
Interchannel Isolation  
(1 kHz)  
-
94  
-
-
95  
-
dB  
Dynamic Performance for CS4334/5/8/9-BS/-DS  
Dynamic Range  
(Note 1)  
unweighted  
A-Weighted  
unweighted  
A-Weighted  
18 to 24-Bit  
16-Bit  
85  
88  
83  
86  
93  
96  
91  
94  
-
-
-
-
-
88  
-
90  
96  
88  
94  
-
-
-
-
dB  
dB  
dB  
dB  
86  
Total Harmonic Distortion + Noise  
18 to 24-Bit  
(Note 1) THD+N  
0 dB  
-20 dB  
-60 dB  
0 dB  
-20 dB  
-60 dB  
-
-
-
-
-
-
-88  
-73  
-33  
-86  
-71  
-31  
-82  
-65  
-25  
-70  
-63  
-23  
-
-
-
-
-
-
-88  
-70  
-30  
-86  
-68  
-28  
-82  
-62  
-22  
-80  
-60  
-20  
dB  
dB  
dB  
dB  
dB  
dB  
16-Bit  
Interchannel Isolation  
(1 kHz)  
-
94  
-
-
95  
-
dB  
Note: 1. One-half LSB of triangular PDF dither added to data.  
DS248F3  
5
CS4334/5/8/9  
ANALOG CHARACTERISTICS (Continued)  
Base-Rate Mode  
Symbol Min Typ Max  
Combined Digital and On-chip Analog Filter Response (Note 2)  
High-Rate Mode  
Min Typ Max Unit  
Parameter  
Passband  
(Note 3)  
to -0.05 dB corner  
to -0.1 dB corner  
to -3 dB corner  
0
-
0
-
-
-
.4780  
-
.4996  
-
0
0
-
-
-
-
Fs  
.4650 Fs  
.4982 Fs  
Frequency Response 10 Hz to 20 kHz  
Passband Ripple  
-.01  
-
+.08  
-.05  
-
+.2  
dB  
dB  
Fs  
dB  
s
-
-
.08  
-
.5770  
55  
-
.2  
-
StopBand  
.5465  
-
-
-
-
-
-
-
StopBand Attenuation  
Group Delay  
(Note 4)  
50  
-
-
-
tgd  
9/Fs  
0.36/Fs  
-
4/Fs  
-
Passband Group Delay Deviation 0 - 40 kHz  
0 - 20 kHz  
-
-
-
1.39/Fs  
0.23/Fs  
-
-
s
s
De-emphasis Error  
Fs = 32 kHz  
Fs = 44.1 kHz  
Fs = 48 kHz  
-
-
-
-
-
-
+1.5/+0  
+.05/-.25  
-.2/-.4  
dB  
dB  
dB  
(Note 5)  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
DC Accuracy  
Interchannel Gain Mismatch  
Gain Error  
-
-
-
0.1  
5
0.4  
dB  
%
-
-
Gain Drift  
100  
ppm/°C  
Analog Output  
Full Scale Output Voltage  
Quiescent Voltage  
Max AC-Load Resistance  
Max Load Capacitance  
3.25  
3.5  
2.2  
3
3.75  
Vpp  
VDC  
kΩ  
V
-
-
-
-
-
-
Q
(Note 6)  
(Note 6)  
R
C
L
L
100  
pF  
Notes: 2. Filter response is not tested but is guaranteed by design.  
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 15-22) have  
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.  
4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.  
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.  
5. De-emphasis is not available in High-Rate Mode.  
6. Refer to Figure 2.  
6
DS248F3  
CS4334/5/8/9  
POWER AND THERMAL CHARACTERISTICS  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
Power Supplies  
Power Supply Current  
normal operation  
power-down state  
I
I
-
-
15  
40  
19  
-
mA  
µA  
A
A
Power Dissipation  
(Note 7)  
normal operation  
power-down  
-
-
75  
0.2  
104  
-
mW  
mW  
Package Thermal Resistance  
Power Supply Rejection Ratio  
θ
-
-
110  
79  
-
-
°C/Watt  
dB  
JA  
(1 kHz)  
PSRR  
Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V.  
10 µF  
V
AOUTx  
out  
R
C
L
L
AGND  
Figure 1. Output Test Load  
125  
100  
75  
70  
65  
60  
55  
M
R
B
75  
50  
25  
Safe Operating  
Region  
50  
20  
2.5  
5
10  
15  
30  
40  
50  
60  
70  
80  
90  
100  
3
Resistive Load -- R (k  
)
L
Sample Rate (kHz)  
Figure 3. Power vs. Sample Rate  
Figure 2. Maximum Loading  
DS248F3  
7
CS4334/5/8/9  
DIGITAL INPUT CHARACTERISTICS  
Parameters  
High-Level Input Voltage  
Low-Level Input Voltage  
Input Leakage Current  
Symbol  
Min  
2.0  
Typ  
-
-
Max  
-
Units  
V
V
IH  
V
I
-
-
-
0.8  
10  
-
V
IL  
(Note 8)  
-
µA  
pF  
in  
Input Capacitance  
8
8. I for CS433X LRCK is 20µA max.  
in  
8
DS248F3  
CS4334/5/8/9  
SWITCHING CHARACTERISTICS  
Parameters  
Symbol  
Min  
2
Typ  
Max  
100  
Units  
kHz  
ns  
Input Sample Rate  
Fs  
-
-
-
-
-
-
-
MCLK Pulse Width High  
MCLK Pulse Width Low  
MCLK/LRCK = 512  
MCLK/LRCK = 512  
10  
10  
21  
21  
31  
31  
1000  
1000  
1000  
1000  
1000  
1000  
ns  
MCLK Pulse Width High MCLK / LRCK = 384 or 192  
MCLK Pulse Width Low MCLK / LRCK = 384 or 192  
MCLK Pulse Width High MCLK / LRCK = 256 or 128  
MCLK Pulse Width Low MCLK / LRCK = 256 or 128  
External SCLK Mode  
ns  
ns  
ns  
ns  
LRCK Duty Cycle (External SCLK only)  
SCLK Pulse Width Low  
40  
20  
20  
50  
60  
-
%
ns  
ns  
ns  
t
-
-
-
sclkl  
SCLK Pulse Width High  
t
-
sclkh  
SCLK Period  
MCLK / LRCK = 512, 256 or 384  
Base-Rate Mode  
High-Rate Mode  
t
-
1
sclkw  
----------------------  
(128)Fs  
SCLK Period  
t
-
-
ns  
1
sclkw  
------------------  
(64)Fs  
MCLK / LRCK = 128 or 192  
SCLK rising to LRCK edge delay  
t
20  
20  
20  
20  
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
slrd  
SCLK rising to LRCK edge setup time  
SDATA valid to SCLK rising setup time  
SCLK rising to SDATA hold time  
Internal SCLK Mode  
t
slrs  
t
sdlrs  
t
sdh  
LRCK Duty Cycle (Internal SCLK only)  
SCLK Period  
(Note 9)  
-
50  
-
-
-
%
(Note 10)  
t
ns  
1
sclkw  
----------------  
SCLK  
SCLK rising to LRCK edge  
t
-
-
µs  
sclkr  
tsclkw  
------------------  
2
SDATA valid to SCLK rising setup time  
SCLK rising to SDATA hold time  
t
-
-
-
ns  
ns  
sdlrs  
1
--------------------- + 10  
(512)Fs  
t
-
-
sdh  
1
--------------------- + 15  
MCLK / LRCK = 512, 256 or 128  
(512)Fs  
SCLK rising to SDATA hold time  
t
-
ns  
sdh  
MCLK / LRCK = 384 or 192  
1
--------------------- + 15  
(384)Fs  
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.  
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK  
ratio. (See figures 10-13)  
DS248F3  
9
CS4334/5/8/9  
LRCK  
t
t
sclkh  
slrs  
t
slrd  
t
sclkl  
SCLK  
t
t
sdh  
sdlrs  
SDATA  
Figure 4. External Serial Mode Input Timing  
LRCK  
t
sclkr  
SDATA  
t
sclkw  
t
t
sdh  
sdlrs  
*INTERNAL SCLK  
Figure 5. Internal Serial Mode Input Timing  
* The SCLK pulses shown are internal to the CS4334/5/8/9.  
LRCK  
MCLK  
N
2
N
1
*INTERNAL SCLK  
SDATA  
Figure 6. Internal Serial Clock Generation  
* The SCLK pulses shown are internal to the CS4334/5/8/9.  
N equals MCLK divided by SCLK  
10  
DS248F3  
CS4334/5/8/9  
2. TYPICAL CONNECTION DIAGRAM  
+5V  
+
0.1 µF  
1 µF  
7
VA  
1
2
3
SDATA  
DEM/SCLK  
LRCK  
3.3 µF  
+
560  
Audio  
Data  
Processor  
8
Left Audio  
Output  
AOUTL  
267 k  
C
R
L
10 k  
CS4334  
CS4335  
CS4338  
CS4339  
3.3 µF  
+
560  
5
AOUTR  
Right Audio  
Output  
4
External Clock  
MCLK  
C
R
L
267 k  
10 k  
R
+ 560  
L
C =  
AGND  
6
π
4 Fs(R 560)  
L
Figure 7. Recommended Connection Diagram  
DS248F3  
11  
CS4334/5/8/9  
filter eliminates images of the baseband audio sig-  
nal which exist at multiples of the input sample  
rate. The resulting frequency spectrum has images  
of the input signal at multiples of 4 Fs. These imag-  
es are easily removed by the on-chip analog low-  
pass filter and a simple external analog filter (see  
Figure 7).  
3. GENERAL DESCRIPTION  
The CS4334 family of devices offers a complete  
stereo digital-to-analog system including digital  
interpolation, fourth-order delta-sigma digital-to-  
analog conversion, digital de-emphasis and analog  
filtering, as shown in Figure 8. This architecture  
provides a high tolerance to clock jitter.  
3.2 Delta-Sigma Modulator  
The primary purpose of using delta-sigma modula-  
tion techniques is to avoid the limitations of resis-  
tive laser trimmed digital-to-analog converter  
architectures by using an inherently linear 1-bit  
digital-to-analog converter. The advantages of a  
1-bit digital-to-analog converter include: ideal dif-  
ferential linearity, no distortion mechanisms due to  
resistor matching errors and no linearity drift over  
time and temperature due to variations in resistor  
values.  
The interpolation filter is followed by a fourth  
order delta-sigma modulator which converts the  
interpolation filter output into 1-bit data at a rate of  
128 Fs in BRM (or 64 Fs in HRM).  
3.3 Switched-Capacitor DAC  
The delta-sigma modulator is followed by a digital-  
to-analog converter which translates the 1-bit data  
into a series of charge packets. The magnitude of  
the charge in each packet is determined by sam-  
pling of a voltage reference onto a switched capac-  
itor, where the polarity of each packet is controlled  
by the 1-bit data. This technique greatly reduces the  
sensitivity to clock jitter and provides low-pass fil-  
tering of the output.  
The CS4334 family of devices supports two modes  
of operation. The devices operate in Base Rate  
Mode (BRM) when MCLK/LRCK is 256, 384 or  
512 and in High Rate Mode (HRM) when  
MCLK/LRCK is 128 or 192. High Rate Mode al-  
lows input sample rates up to 100 kHz.  
3.4 Analog Low-Pass Filter  
3.1 Digital Interpolation Filter  
The final signal stage consists of a continuous-time  
low-pass filter which serves to smooth the output  
and attenuate out-of-band noise.  
The digital interpolation filter increases the sample  
rate, Fs, by a factor of 4 and is followed by a  
32× digital sample-and-hold (16× in HRM). This  
Analog  
Analog  
Digital  
Input  
Delta-Sigma  
Modulator  
Interpolator  
DAC  
Low-Pass  
Filter  
Output  
Figure 8. System Block Diagram  
12  
DS248F3  
CS4334/5/8/9  
4. SYSTEM DESIGN  
4.2.1 External Serial Clock Mode  
The CS4334 family accepts data at standard audio  
sample rates including 48, 44.1 and 32 kHz in  
BRM and 96, 88.2 and 64 kHz in HRM. Audio data  
is input via the serial data input pin (SDATA). The  
Left/Right Clock (LRCK) defines the channel and  
delineation of data, and the Serial Clock (SCLK)  
clocks audio data into the input data buffer. The  
CS4334/5/8/9 differ in serial data formats as shown  
in Figures 10-13.  
The CS4334 family will enter the External Serial  
Clock Mode when 16 low to high transitions are  
detected on the DEM/SCLK pin during any phase  
of the LRCK period. When this mode is enabled,  
the Internal Serial Clock Mode and de-emphasis  
filter cannot be accessed. The CS4334 family will  
switch to Internal Serial Clock Mode if no low to  
high transitions are detected on the DEM/SCLK  
pin for 2 consecutive frames of LRCK. Refer to  
Figure 14.  
4.1 Master Clock  
4.2.2 Internal Serial Clock Mode  
MCLK must be either 256x, 384x or 512x the de-  
sired input sample rate in BRM and either 128x or  
192x the desired input sample rate in HRM. The  
LRCK frequency is equal to Fs, the frequency at  
which words for each channel are input to the de-  
vice. The MCLK-to-LRCK frequency ratio is de-  
tected automatically during the initialization  
sequence by counting the number of MCLK transi-  
tions during a single LRCK period. Internal divid-  
ers are set to generate the proper clocks. Table 1  
illustrates several standard audio sample rates and  
the required MCLK and LRCK frequencies. Please  
In the Internal Serial Clock Mode, the serial clock  
is internally derived and synchronous with MCLK  
and LRCK. The SCLK/LRCK frequency ratio is ei-  
ther 32, 48, or 64 depending upon data format. Op-  
eration in this mode is identical to operation with  
an external serial clock synchronized with LRCK.  
This mode allows access to the digital de-emphasis  
function. Refer to Figures 10 - 14 for details.  
4.3 De-Emphasis  
The CS4334 family includes on-chip digital de-em-  
note there is no required phase relationship, but phasis. Figure 9 shows the de-emphasis curve for  
MCLK, LRCK and SCLK must be synchronous.  
Fs equal to 44.1 kHz. The frequency response of  
the de-emphasis curve will scale proportionally  
with changes in sample rate, Fs.  
MCLK (MHz)  
LRCK  
(kHz)  
HRM  
128x 192x  
BRM  
384x  
256x  
512x  
The de-emphasis filter is active (inactive) if the  
DEM/SCLK pin is low (high) for 5 consecutive  
falling edges of LRCK. This function is available  
only in the internal serial clock mode.  
32  
44.1  
48  
4.0960 6.1440 8.1920 12.2880 16.3840  
5.6448 8.4672 11.2896 16.9344 22.5792  
6.1440 9.2160 12.2880 18.4320 24.5760  
64  
8.1920 12.2880  
-
-
-
-
-
-
-
-
-
Gain  
dB  
88.2 11.2896 16.9344  
96 12.2880 18.4320  
T1=50 µs  
0dB  
Table 1. Common Clock Frequencies  
4.2 Serial Clock  
T2 = 15 µs  
-10dB  
The serial clock controls the shifting of data into  
the input data buffers. The CS4334 family supports  
both external and internal serial clock generation  
modes. Refer to Figures 10-13 for data formats.  
F1  
3.183 kHz  
F2  
10.61 kHz  
Frequency  
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)  
DS248F3  
13  
CS4334/5/8/9  
complished by removing MCLK or LRCK. When  
this occurs, audio output ceases and the internal  
output buffers are disconnected from AOUTL and  
AOUTR. A soft-start current sink is substituted in  
place of AOUTL and AOUTR which allows the  
DC-blocking capacitors to slowly discharge. Once  
this charge is dissipated, the power to the device  
may be turned off, and the system is ready for the  
next power-on.  
4.4 Initialization and Power-Down  
The Initialization and Power-Down sequence flow  
chart is shown in Figure 14. The CS4334 family en-  
ters the Power-Down State upon initial power-up.  
The interpolation filters and delta-sigma modula-  
tors are reset, and the internal voltage reference,  
one-bit digital-to-analog converters and switched-  
capacitor low-pass filters are powered down. The  
device will remain in the Power-Down mode until  
MCLK and LRCK are present. Once MCLK and  
LRCK are detected, MCLK occurrences are count-  
ed over one LRCK period to determine the  
MCLK/LRCK frequency ratio. Power is then ap-  
To prevent an audio transient at the next power-on,  
the DC-blocking capacitors must fully discharge  
before turning off the power or exiting the power-  
down state. If full discharge does not occur, a tran-  
plied to the internal voltage reference. Finally, pow- sient will occur when the audio outputs are initially  
er is applied to the D/A converters and switched- clamped to AGND. The time that the device must  
capacitor filters, and the analog outputs will ramp to remain in the power-down state is related to the  
the quiescent voltage, V .  
value of the DC-blocking capacitance. For exam-  
ple, with a 3.3 µF capacitor, the time that the device  
must remain in the power-down state will be ap-  
proximately 0.4 seconds.  
Q
4.5 Output Transient Control  
The CS4334 family uses Popguard® technology to  
minimize the effects of output transients during  
power-up and power-down. This technique elimi-  
nates the audio transients commonly produced by  
single-ended single-supply converters when it is  
implemented with external DC-blocking capacitors  
connected in series with the audio outputs. To  
make best use of this feature, it is necessary to un-  
derstand its operation.  
4.6 Grounding and Power Supply  
Decoupling  
As with any high resolution converter, the CS4334  
family requires careful attention to power supply  
and grounding arrangements to optimize perfor-  
mance. Figure 7 shows the recommended power ar-  
rangement with VA connected to a clean +5V  
supply. For best performance, decoupling capaci-  
tors should be located as close to the device pack-  
age as possible with the smallest capacitor closest.  
When the device is initially powered-up, the audio  
outputs, AOUTL and AOUTR, are clamped to  
AGND. After a short delay of approximately 1000  
sample periods, each output begins to ramp to-  
wards its quiescent voltage, V . Approximately  
10,000 sample cycles later, the outputs reach V  
4.7 Analog Output and Filtering  
Q
The analog filter present in the CS4334 family is a  
switched-capacitor filter followed by a continuous  
time low pass filter. Its response, combined with  
that of the digital interpolator, is given in Figures  
15 - 22.  
Q
and audio output begins. This gradual voltage  
ramping allows time for the external DC-blocking  
capacitor to charge to V , effectively blocking the  
Q
quiescent DC voltage.  
To prevent transients at power-down, the device  
must first enter its power-down state. This is ac-  
14  
DS248F3  
CS4334/5/8/9  
Left Channel  
Right Channel  
LRCK  
SCLK  
SDATA  
+5 +4 +3 +2 +1 LSB  
+5 +4 +3 +2 +1 LSB  
MSB -1 -2 -3 -4 -5  
MSB -1 -2 -3 -4  
Internal SCLK Mode  
External SCLK Mode  
2
2
I S, 16-Bit data and INT SCLK = 32 Fs if  
MCLK/LRCK = 512, 256 or 128  
I S, Up to 24-Bit data and INT SCLK = 48 Fs if  
I S, up to 24-Bit Data  
Data Valid on Rising Edge of SCLK  
2
MCLK/LRCK = 384 or 192  
2
Figure 10. CS4334 Data Format (I S)  
Left Channel  
Right Channel  
LRCK  
SCLK  
SDATA  
+5 +4 +3 +2 +1 LSB  
+5 +4 +3 +2 +1 LSB  
MSB -1 -2 -3 -4 -5  
MSB -1 -2 -3 -4  
Internal SCLK Mode  
External SCLK Mode  
Left Justified, up to 24-Bit Data  
Data Valid on Rising Edge of SCLK  
Left Justified, up to 24-Bit Data  
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128  
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192  
Figure 11. CS4335 Data Format  
Right Channel  
LRCK  
Left Channel  
SCLK  
SDATA  
15 14 13 12 11 10  
32 clocks  
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  
Internal SCLK Mode  
Right Justified, 16-Bit Data  
External SCLK Mode  
Right Justified, 16-Bit Data  
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128  
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192  
Data Valid on Rising Edge of SCLK  
SCLK Must Have at Least 32 Cycles per LRCK Period  
Figure 12. CS4338 Data Format  
DS248F3  
15  
CS4334/5/8/9  
Right Channel  
LRCK  
SCLK  
Left Channel  
SDATA  
1
0
17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  
32 clocks  
Internal SCLK Mode  
External SCLK Mode  
Right Justified, 18-Bit Data  
Right Justified, 18-Bit Data  
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128  
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192  
Data Valid on Rising Edge of SCLK  
SCLK Must Have at Least 36 Cycles per LRCK Period  
Figure 13. CS4339 Data Format  
16  
DS248F3  
CS4334/5/8/9  
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence  
DS248F3  
17  
CS4334/5/8/9  
4.8 Overall Base-Rate Frequency Response  
Figure 15. Stopband Rejection  
Figure 16. Transition Band  
Figure 17. Transition Band  
Figure 18. Passband Ripple  
18  
DS248F3  
CS4334/5/8/9  
4.9 Overall High-Rate Frequency Response  
Figure 19. Stopband Rejection  
Figure 20. Transition Band  
Figure 21. Transition Band  
Figure 22. Passband Ripple  
DS248F3  
19  
CS4334/5/8/9  
4.10 Base Rate Mode Performance Plots  
+0  
+0  
+0  
-10  
-10  
-20  
-20  
-30  
-30  
-40  
-40  
-50  
-50  
-60  
-60  
-70  
-80  
-70  
-80  
-90  
-90  
-100  
-100  
-110  
-110  
-120  
-120  
-130  
-130  
-140  
2k  
4k  
6
8k  
10k  
12
14k  
16k  
18k  
20k  
-140  
4k  
18k 20k  
2k  
6k  
8k  
10k  
12k  
14k  
16k  
2k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
20k  
Hz  
Hz  
(16k FFT of a 1 kHz input signal)  
(16k FFT of a 1 kHz input signal)  
Figure 23. 0 dBFS FFT (BRM)  
Figure 24. -60 dBFS FFT (BRM)  
+ 0  
+0  
+0
+0  
-10
-10  
-20
-20  
-30
-30  
-40  
-40
-50  
-50  
-60  
-60  
-70  
-70  
-80  
-80  
-90  
-90  
-100  
-100  
-110  
-110  
-120  
-120  
-130  
-130  
-140  
20k  
-140
2
k
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
20k  
16k  
18k  
2k  
4k  
6k  
8k  
10k  
12k  
14k  
Hz  
Hz  
(16k FFT with no input signal)  
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)  
Figure 25. Idle Channel Noise FFT (BRM)  
Figure 26. Twin Tone IMD FFT (BRM)  
-60  
+0  
+0  
-10  
-70  
-20  
-30  
-40  
-80  
-50  
-60  
-90  
-70
-80  
-100  
-90  
-100  
-110  
6
0
-
5
0
-4
0
-
3
0
-
2
0
-
1
0
+0  
-110
0  
50  
50  
100  
200  
200  
500  
1k  
1k  
2k  
2k  
5k  
5k  
10k  
20k  
20k  
20  
20  
500  
10k  
100  
dBFS  
Hz  
(THD+N plots measured using a 1kHz 24-bit dithered input signal)  
(THD+N plots measured using a 1kHz 24-bit dithered input signal)  
Figure 27. THD+N vs. Amplitude (BRM)  
Figure 28. THD+N vs. Frequency (BRM)  
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain  
System Two Cascade.  
20  
DS248F3  
CS4334/5/8/9  
4.11 High Rate Mode Performance Plots  
+0  
+0  
+0  
-10  
-10  
-20  
-2
0
-30  
-30  
-40  
-40
-50  
-50
-60  
-60  
-70  
-70  
-80
-80  
-90
-90  
-100  
-100  
-110
-10
-120  
-120  
-1
-1
-130
3
0
-140
4
0
2k  
2k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
20k  
0k  
20k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
18k 20k  
4k  
2k  
6k  
8k  
10k  
12k  
14k  
16k  
Hz  
Hz  
(16k FFT of a 1 kHz input signal)  
(16k FFT of a 1 kHz input signal)  
Figure 29. 0 dBFS FFT (HRM)  
Figure 30. -60 dBFS FFT (HRM)  
Audio Precision  
D-A CCIF IMD vs AMPLITUDE  
08/05/99 11:11:36  
+0  
+0  
+0  
+0  
-10  
-10  
-20
-20  
-30
-30  
-40
-40  
-50  
-50  
-60  
-60  
-7
0
-70  
-80  
-80  
-90  
-90
-100  
-100  
-1
1
0
-110  
-120  
-120  
-1
-1
-130  
3
0
-140  
4
0
2k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
20k  
2k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
18k  
20k  
20k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
2k  
4k  
6k  
8k  
10k  
12k  
14k  
16k  
18k  
20k  
Hz  
Hz  
(16k FFT with no input signal)  
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)  
Figure 31. Idle Channel Noise FFT (HRM)  
Figure 32. Twin Tone IMD FFT (HRM)  
-60  
+0  
-10  
-20  
-70  
-30  
-40  
-80  
-50  
-60  
-90  
-70  
-80  
-100  
-90  
-100  
-60  
-110  
-110  
-50  
-50  
-4
-40  
-30  
-2
-20  
-0  
-10  
+0  
+0  
-30  
0  
50  
100  
200  
500  
1
2k  
5k  
10k 20k  
10k 20k  
20  
50  
200  
5001k  
2k  
5k  
100  
dBFS  
Hz  
(THD+N plots measured using a 1kHz 24-bit dithered input signal)  
(THD+N plots measured using a 1kHz 24-bit dithered input signal)  
Figure 33. THD+N vs. Amplitude (HRM)  
Figure 34. THD+N vs. Frequency (HRM)  
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain  
System Two Cascade.  
DS248F3  
21  
CS4334/5/8/9  
5. PIN DESCRIPTIONS  
SERIAL DATA INPUT  
DE-EMPHASIS / SCLK  
LEFT / RIGHT CLOCK  
MASTER CLOCK  
SDATA  
DEM/SCLK  
LRCK  
1
2
3
4
8
7
6
5
AOUTL  
VA  
ANALOG LEFT CHANNEL OUTPUT  
ANALOG POWER  
AGND  
AOUTR  
ANALOG GROUND  
MCLK  
ANALOG RIGHT CHANNEL OUTPUT  
No. Pin Name I/O  
Pin Function and Description  
1
SDATA  
I
Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin.  
The data is clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel  
is determined by LRCK.  
2
3
4
DEM/SCLK  
LRCK  
I
I
I
De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter-  
nal serial clock input.  
Left/Right Clock - determines which channel is currently being input on the Audio Serial  
Data Input pin, SDATA.  
Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and  
either 128x or 192x the input sample rate in HRM.  
MCLK  
5
6
7
8
AOUTR  
AGND  
VA  
O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal.  
I
I
Analog Ground - analog ground reference is 0V.  
Analog Power - analog power supply is nominally +5V.  
AOUTL  
O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.  
22  
DS248F3  
CS4334/5/8/9  
6. PARAMETER DEFINITIONS  
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the  
rms sum of all other spectral components over the specified bandwidth (typically 10Hz to  
20kHz), including distortion components. Expressed in decibels.  
Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other  
spectral components over the specified bandwidth. Dynamic range is a signal-to-noise  
measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added  
to the resulting measurement to refer the measurement to full scale. This technique ensures that  
the distortion components are below the noise level and do not effect the measurement. This  
measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and  
the Electronic Industries Association of Japan, EIAJ CP-307.  
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured  
for each channel at the converter's output with all zeros to the input under test and a full-scale  
signal applied to the other channel. Units in decibels.  
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in  
decibels.  
Gain Error - The deviation from the nominal full scale analog output for a full scale digital  
input.  
Gain Drift - The change in gain value with temperature. Units in ppm/°C.  
7. REFERENCES  
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.  
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.  
2) CDB4334/5/8/9 Evaluation Board Datasheet  
DS248F3  
23  
CS4334/5/8/9  
8. ORDER INFORMATION:  
Model  
CS4334-KS  
CS4335-KS  
CS4334-KSZ  
CS4335-KSZ  
CS4338-KS  
CS4339-KS  
CS4334-BS  
CS4339-BS  
CS4334-DS  
CS4335-DS  
CS4338-DS  
CS4339-DS  
Temperature  
-10 to +70 °C  
-10 to +70 °C  
-10 to +70 °C  
-10 to +70 °C  
-10 to +70 °C  
-10 to +70 °C  
-40 to +85 °C  
-40 to +85 °C  
-40 to +85 °C  
-40 to +85 °C  
-40 to +85 °C  
-40 to +85 °C  
Package  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
Serial Interface  
16 to 24-bit, I2S  
16 to 24-bit, left justified  
8-pin Plastic SOIC, lead free 16 to 24-bit, I2S  
8-pin Plastic SOIC, lead free 16 to 24-bit, left justified  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
8-pin Plastic SOIC  
16-bit, right justified  
18-bit, right justified, 32 F Internal SCLK mode  
s
16 to 24-bit, I2S  
18-bit, right justified, 32 F Internal SCLK mode  
s
16 to 24-bit, I2S  
16 to 24-bit, left justified  
16-bit, right justified  
18-bit, right justified, 32 F Internal SCLK mode  
s
9. FUNCTIONAL COMPATIBILITY  
CS4330-KS CS4339-KS  
CS4331-KS CS4334-KS  
CS4333-KS CS4338-KS  
CS4330-BS  
CS4331-BS  
CS4333-BS  
CS4339-BS/-DS  
CS4334-BS/-DS  
CS4338-DS  
Revision Date  
Changes  
F3  
July 2004  
Removed CS4335-BS and CS4339-BS from the Ordering Information section.  
Table 2. Revision History  
24  
DS248F3  
CS4334/5/8/9  
10. PACKAGE DIMENSIONS  
8L SOIC (150 MIL BODY) PACKAGE DRAWING  
E
H
1
b
c
D
SEATING  
PLANE  
A
L
e
A1  
INCHES  
MILLIMETERS  
MIN  
DIM  
A
A1  
B
C
D
E
e
H
L
MIN  
0.053  
0.004  
0.013  
0.007  
0.189  
0.150  
0.040  
0.228  
0.016  
0°  
MAX  
0.069  
0.010  
0.020  
0.010  
0.197  
0.157  
0.060  
0.244  
0.050  
8°  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
1.52  
6.20  
1.27  
8°  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
1.02  
5.80  
0.40  
0°  
JEDEC # : MS-012  
DS248F3  
25  
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