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产品型号CS8101YDWFR20的Datasheet PDF文件预览

CS8101

Micropower 5V, 100mA Low Dropout

Linear Regulator with RESET and ENABLE

Features

■ 5V ±2% Output

Description

The CS8101 is a precision 5V

normal operation if the output

micropower voltage regulator with

very low quiescent current (70µA

typ at 100µA load). The 5V output is logic level compatible

accurate within ±2% and supplies

100mA of load current with a typi-

cal dropout voltage of only 400mV.

Microprocessor control logic

voltage drops outside the regulation

limits by more than 200mV typ. The

■ Low 70µA Quiescent

Current

ENABLE

■ Active RESET

input allows the user to put the reg-

ulator into a shutdown mode where

it draws only 20µA typical of quies-

cent current.

■

ENABLE Input for

ON/OFF and Active/Sleep

Mode Control

ENABLE

RESET

includes an

active

input and an

. This combination of

The regulator is protected against

reverse battery, short circuit, over

voltage, and thermal overload con-

ditions. The device can withstand

load dump transients making it

suitable for use in automotive envi-

ronments.

■ 100mA Output Current

Capability

low quiescent current, outstanding

regulator performance and control

logic makes the CS8101 ideal for

any battery operated, microproces-

sor controlled equipment.

■ Fault Protection

+60V Peak Transient

Voltage

-15V Reverse Voltage

Short Circuit

RESET

The active

circuit includes

The CS8101 is functionally equiva-

lent to the National Semiconductor

LP2951 series low current regula-

tors.

Thermal Overload

hysteresis, and operates correctly at

an output voltage as low as 1V. The

■ Low Reverse Current

RESET

function is activated during

the power up sequence or during

(Output to Input)

Package Options

Block Diagram

20L SOIC Wide

(Internally Fused Leads)

ENABLE

OUT

Gnd

Over

Current Source

(Circuit Bias)

Voltage

Shutdown

Internally connected

on 5 lead TO-220

ENABLE

Current Limit

Sense

RESET

Sense

OUT

8L SOIC

5L TO-220

Tab (Gnd)

Error

Amplifier

OUT

Sense

OUT

Thermal

Protection

ENABLE

Gnd

RESET

Bandgap

Reference

1. V_OUT

ENABLE

3. Gnd

4. RESET

5. V_IN

RESET

Gnd

Reset

Comparator

Other Packages: D²PAK (consult factory)

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786

Email: info@cherry-semi.com

Web Site: www.cherry-semi.com

Rev. 4/9/99

Company

Absolute Maximum Ratings

Power Dissipation.............................................................................................................................................Internally Limited

Transient Peak Voltage (46V Load Dump) ..................................................................................................................-15V, 60V

Output Current .................................................................................................................................................Internally Limited

ESD Susceptibility (Human Body Model) ..............................................................................................................................2kV

Operating Temperature..........................................................................................................................................-40¡C to 125¡C

Junction Temperature.............................................................................................................................................-40¡C to 150¡C

Storage Temperature ................................................................................................................................................-55C to 150¡C

Lead Temperature Soldering Wave Solder (through hole styles only) ..........................................10 sec. max, 260¡C peak

Reflow (SMD styles only) ..........................................60 sec. max above 183¡C, 230¡C peak

Electrical Characteristics: 6V ² V_IN² 26V, I_OUT= 1mA, -40 ² T_A² 125, -40 ² T_J² 150¡C unless otherwise specified.

PARAMETER

■ Output Stage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output Voltage, V_OUT

9V < V_IN< 16V, 100µA ² I_OUT² 100mA

6V ² V_IN² 26V, 100µA ² I_OUT² 100mA

4.90

4.85

5.00

5.10

5.15

Dropout Voltage (V_IN-V_OUT

)

I_OUT= 100mA

400

100

600

150

I_OUT= 100µA

Load Regulation

Line Regulation

V_IN= 14V, 100µA ² I_OUT² 100mA

6V < V < 26V, I_OUT= 1mA

Quiescent Current, (I_Q)

Active Mode

I_OUT= 100µA, V_IN= 6V

I_OUT= 50mA

I_OUT² 100mA

140

µA

Sleep Mode

V_OUT= OFF, V_IN= 6V, V_ENABLE= 2V

µA

¡C

Ripple Rejection

Current Limit

7 ² V_IN² 17V, I_OUT= 100mA, f = 120Hz

105

200

125

180

Short Circuit Output Current V_OUT= 0V

Thermal Shutdown

150

Overvoltage Shutdown

Reverse Current

V_OUT² 1V

V_OUT= 5V, V_IN= 0V

100

200

µA

■ Enable Input ( ENABLE )

Threshold

HIGH

(V_OUTOFF)

(V_OUTON)

1.4

2.0

LOW

0.6

Input Current

V_ENABLE= 2.4V

100

µA

■ Reset Function ( RESET )

RESET

Threshold

HIGH (V_RH

LOW (V_RL

RESET

)

V_OUTIncreasing

V_OUTDecreasing

4.525

4.500

4.75

4.700

V_OUT- 0.05

V_OUT- 0.075

)

Hysteresis

Reset Output Leakage

RESET

(HIGH - LOW)

V_OUT³ V_RH

100

µA

= HIGH

Output Voltage

Low (V_RLO

)

1V ² V_OUT² V_RL

0.1

0.6

0.4

1.0

R_RESET= 10K

Low (VRpeak)

V_OUT, Power up, Power down

Package Lead Description

LEAD SYMBOL

PACKAGE LEAD #

20 Lead SOIC

FUNCTION

8 Lead

5 Lead

SOIC (Internally Fused Leads) TO-220

V_IN

Input voltage.

5V, ±2%, 100mA output.

V_OUT

ENABLE

Gnd

Logic level switches output off when toggled HIGH.

Ground. All Gnd leads must be connected to Ground.

4,5,6,7

14,15,16,17

RESET

Active reset (accurate to V_OUT³ 1V).

V_OUTSense

Kelvin connection which allows remote sensing of out-

put voltage for improved regulation. If remote sensing

is not required, connect to V_OUT

6,7

2,3,8,9,11,12,13,18

No Connection.

Circuit Description

Voltage Reference and Output Circuitry

Output Stage Protection

FOR 7V < V < 26V

The output stage is protected against overvoltage, short

circuit and thermal runaway conditions (Figure 1).

ENABLE

> 30V

V_RH

V_RL

OUT

(1)

PEAK

(2)

VR_LO

RESET

(1) = NO RESET DELAY CAPACITOR

(2) = WITH RESET DELAY CAPACITOR

OUT

Load

Dump

Current

Limit

Short

Circuit

Figure 2. Circuit Waveform

ENABLE

The

and OFF. When the voltage on the

1.4V typ, the output pass transistor turns off, leaving a

high impedance facing the load. The IC will remain in

Sleep mode, drawing only 50µA, until the voltage on this

Function

function switches the output transistor ON

ENABLE

Figure 1. Typical Circuit Waveforms for Output Stage Protection.

ENABLE

If the input voltage rises above 30V (e.g. load dump), the out-

put shuts down. This response protects the internal circuitry

and enables the IC to survive unexpected voltage transients.

lead exceeds

Should the junction temperature of the power device exceed

180ûC (typ) the load current capability is reduced thereby

preventing thermal overload. This thermal management

function is an effective means to prevent die overheating

since the load current is the principle heat source in the IC.

ENABLE

input drops below the

threshold.

RESET

Function

RESET

signal (low voltage) is generated as the IC pow-

ers up until V_OUTis within 250mV of the regulated output

voltage, or when V_OUTdrops out of regulation,and is

lower than 300mV below the regulated output voltage. A

hysteresis of 50mV is included in the function to minimize

oscillations.

Regulator Control Functions

The CS8101 contains two microprocessor compatible con-

ENABLE

RESET

(Figure 2).

trol functions:

and

RESET

The

output is an open collector NPN transistor,

controlled by a low voltage detection circuit. The circuit is

functionally independent of the rest of the IC thereby

RESET

guaranteeing that the

as 1V.

signal is valid for V_OUTas low

Circuit Description: continued

based applications. RC values can be chosen using the

following formula:

Ðt_Delay

V_OUT

5V to mP

and

R_TOTC_RST

System

Power

V_TÐ V_OUT

V_RSTÐ V_OUT

OUT

[

]

RST

CS8101

)

(

to mP

RESET

Port

RESET

where: R_RST

Delay resistor

RST

R_IN= µP port impedance

R_TOT= R_RSTin parallel with R_IN

RESET

Delay capacitor

C_RST

t_Delay= desired delay time

RESET

Figure 3. RC Network for RESET Delay

V_RST= V_SATof

lead (0.7V @ turn - ON)

threshold

RESET

An external RC network on the

lead (Figure 3) pro-

RESET

V_T

vides a sufficiently long delay for most microprocessor

Applications Notes

V_IN

V_OUT

BAT

0.1mF

OUT

500kW

RST

CS8101

RESET

ENABLE

Gnd

I/O Port

RST

100kW

500kW

100kW

SWITCH

Figure 4. Microprocessor Control of CS8101 using external switching transistor Q .

The circuit depicted in Figure 4 lets the microprocessor

ENABLE

By coupling these two controls with the

lead, the

control its power source, the CS8101 regulator. An I/O

port on the µP and the SWITCH port are used to drive the

base of Q1. When Q1 is driven into saturation, the voltage

system has added flexibility. Once the system is running,

the state of the SWITCH is irrelevant as long as the I/O

port continues to drive Q1. The microprocessor can turn

off its own power by withdrawing drive current, once the

SWITCH is open. This software control at the I/O port

allows the microprocessor to finish key housekeeping

functions before power is removed.

ENABLE

on the

lead falls below its lower threshold. The

regulatorÕs output is

removed, the voltage on the

. When the drive current is

enabled

ENABLE

lead rises, the out-

put is switched off and the IC moves into Sleep mode

where it draws 50µA (max).

The logic options are summarized in Table 1.

Application Notes: continued

increase the load current slowly from zero to full load

Table 1. Logic Control of CS8101 Output

Microprocessor

while observing the output for any oscillations. If no oscil-

lations are observed, the capacitor is large enough to

ensure a stable design under steady state conditions.

I/O drive

Switch

Closed

Open

ENABLE

LOW

Output

Step 3: Increase the ESR of the capacitor from zero using

the decade box and vary the load current until oscillations

appear. Record the values of load current and ESR that

cause the greatest oscillation. This represents the worst

case load conditions for the regulator at low temperature.

OFF

Closed

Open

LOW

HIGH

OFF

Step 4: Maintain the worst case load conditions set in step

3 and vary the input voltage until the oscillations increase.

This point represents the worst case input voltage conditions.

The I/O port of the microprocessor typically provides

50µA to Q1. In automotive applications the SWITCH is

connected to the ignition switch.

Step 5: If the capacitor is adequate, repeat steps 3 and 4

with the next smaller valued capacitor. A smaller capacitor

will usually cost less and occupy less board space. If the

output oscillates within the range of expected operating

conditions, repeat steps 3 and 4 with the next larger stan-

dard capacitor value.

Stability Considerations

The output or compensation capacitor helps determine

three main characteristics of a linear regulator: start-up

delay, load transient response and loop stability.

Step 6: Test the load transient response by switching in

various loads at several frequencies to simulate its real

working environment. Vary the ESR to reduce ringing.

V_IN

V_OUT

Step 7: Remove the unit from the environmental chamber

and heat the IC with a heat gun. Vary the load current as

instructed in step 5 to test for any oscillations.

0.1mF

OUT

RST

10mF

CS8101

RESET

Once the minimum capacitor value with the maximum

ESR is found, a safety factor should be added to allow for

the tolerance of the capacitor and any variations in regula-

tor performance. Most good quality aluminum electrolytic

capacitors have a tolerance of ±20% so the minimum value

found should be increased by at least 50% to allow for this

tolerance plus the variation which will occur at low tem-

peratures. The ESR of the capacitor should be less than

50% of the maximum allowable ESR found in step 3 above.

ENABLE

*C required if regulator is located far from the power supply filter.

OUT

**C

required for stability. Capacitor must operate at minimum

temperature expected.

Figure 5. Test and application circuit showing output compensation.

Calculating Power Dissipation

in a Single Output Linear Regulator

The capacitor value and type should be based on cost,

availability, size and temperature constraints. A tantalum

or aluminum electrolytic capacitor is best, since a film or

ceramic capacitor with almost zero ESR can cause instabili-

ty. The aluminum electrolytic capacitor is the least expen-

sive solution, but, if the circuit operates at low tempera-

tures (-25¡C to -40¡C), both the value and ESR of the

capacitor will vary considerably. The capacitor manufac-

turers data sheet usually provides this information.

The maximum power dissipation for a single output regu-

lator (Figure 6) is:

P_D(max)= V_IN(max)- V_OUT(min)_}

_OUT(max)+ V_{IN(max) Q}

(1)

{

where:

V_IN(max)is the maximum input voltage,

V_OUT(min)is the minimum output voltage,

The value for the output capacitor C_OUTshown in Figure 5

should work for most applications, however it is not nec-

essarily the optimized solution.

I_OUT(max)is the maximum output current for the applica-

tion, and

I_Qis the quiescent current the regulator consumes at

I_OUT(max)

To determine an acceptable value for C_OUTfor a particular

application, start with a tantalum capacitor of the recom-

mended value and work towards a less expensive alterna-

tive part.

Once the value of P_D(max)is known, the maximum permis-

sible value of R_QJAcan be calculated:

Step 1: Place the completed circuit with a tantalum capac-

itor of the recommended value in an environmental cham-

ber at the lowest specified operating temperature and

monitor the outputs with an oscilloscope. A decade box

connected in series with the capacitor will simulate the

higher ESR of an aluminum capacitor. Leave the decade

box outside the chamber, the small resistance added by the

longer leads is negligible.

150¡C - T_A

(2)

R_QJA

P_D

The value of R_QJAcan then be compared with those in

the package section of the data sheet. Those packages with

_QJA's less than the calculated value in equation 2 will keep

the die temperature below 150¡C.

Step 2: With the input voltage at its maximum value,

Application Notes: continued

In some cases, none of the packages will be sufficient to

Heatsinks

dissipate the heat generated by the IC, and an external

heatsink will be required.

A heatsink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed

OUT

Smart

Regulator

OUT

to determine the value of R_QJA

Control

Features

_QJA= R_QJC+ R_QCS+ R_QSA

(3)

}

where:

_QJC= the junctionÐtoÐcase thermal resistance,

_QCS= the caseÐtoÐheatsink thermal resistance, and

_QSA= the heatsinkÐtoÐambient thermal resistance.

_QJCappears in the package section of the data sheet. Like

_QJA, it too is a function of package type. R_QCSand R_QSA

Figure 6: Single output regulator with key performance parameters

labeled.

are functions of the package type, heatsink and the inter-

face between them. These values appear in heatsink data

sheets of heatsink manufacturers.

Package Specification

PACKAGE DIMENSIONS IN mm (INCHES)

PACKAGE THERMAL DATA

8 Lead

20 Lead

5 Lead

Lead Count

Metric

English

Thermal Data SOIC SOIC Wide TO-220

Max

5.00

13.00 12.60

Min

4.80

Max Min

R_QJC

R_QJA

typ

3.3

ûC/W

8L SOIC

20L SOIC

.197

.512

.189

.496

165

Surface Mount Narrow Body (D); 150 mil wide

6.20 (.244)

5.80 (.228)

4.00 (.157)

3.80 (.150)

0.51 (.020)

0.33 (.013)

1.27 (.050) BSC

1.75 (.069) MAX

1.57 (.062)

1.37 (.054)

0.25 (.010)

0.19 (.008)

1.27 (.050)

0.40 (.016)

0.25 (0.10)

0.10 (.004)

REF: JEDEC MS-012

Surface Mount Wide Body (DW); 300 mil wide

7.60 (.299)

7.40 (.291)

10.65 (.419)

10.00 (.394)

0.51 (.020)

0.33 (.013)

1.27 (.050) BSC

2.49 (.098)

2.24 (.088)

2.65 (.104)

2.35 (.093)

0.32 (.013)

0.23 (.009)

1.27 (.050)

0.40 (.016)

0.30 (.012)

0.10 (.004)

REF: JEDEC MS-013

Package Specification

5 Lead TO-220 (T) Straight

5 Lead TO-220 (THA) Horizontal

4.83 (.190)

4.06 (.160)

10.54 (.415)

9.78 (.385)

1.40 (.055)

1.14 (.045)

3.96 (.156)

3.71 (.146)

1.40 (.055)

1.14 (.045)

2.87 (.113)

2.62 (.103)

4.83 (.190)

4.06 (.160)

10.54 (.415)

9.78 (.385)

3.96 (.156)

3.71 (.146)

14.99 (.590)

14.22 (.560)

2.87 (.113)

2.62 (.103)

6.55 (.258)

5.94 (.234)

6.55 (.258)

5.94 (.234)

14.99 (.590)

14.22 (.560)

2.77 (.109)

6.83 (.269)

1.68

14.22 (.560)

13.72 (.540)

2.92 (.115)

2.29 (.090)

0.56 (.022)

(.066)

TYP

0.81(.032)

0.36 (.014)

6.60 (.260)

5.84 (.230)

1.70 (.067)

6.81(.268)

1.02 (.040)

0.76 (.030)

0.56 (.022)

0.36 (.014)

1.83(.072)

1.57(.062)

1.02(.040)

0.63(.025)

6.93(.273)

6.68(.263)

2.92 (.115)

2.29 (.090)

5 Lead TO-220 (TVA) Vertical

4.83 (.190)

4.06 (.160)

3.96 (.156)

3.71 (.146)

10.54 (.415)

9.78 (.385)

1.40 (.055)

1.14 (.045)

6.55 (.258)

5.94 (.234)

2.87 (.113)

2.62 (.103)

14.99 (.590)

14.22 (.560)

1.78 (.070)

2.92 (.115)

2.29 (.090)

8.64 (.340)

7.87 (.310)

4.34 (.171)

7.51 (.296)

0.56 (.022)

0.36 (.014)

1.68

(.066) typ

1.70 (.067)

6.80 (.268)

.94 (.037)

.69 (.027)

Ordering Information

Part Number

CS8101YD8

Description

8L SOIC

CS8101YDR8

CS8101YDWF20

CS8101YDWFR20

8L SOIC (tape & reel)

20L SOIC (internally fused leads)

(tape & reel)

CS8101YT5

CS8101YTVA5

CS8101YTHA5

5L TO-220

5L TO-220 Vertical

5L TO-220 Horizontal

Ch erry Sem icon du ctor Corporation reserves th e

righ t to m ake ch an ges to th e specification s with ou t

n otice. Please con tact Ch erry Sem icon du ctor

Corporation for th e latest available in form ation .

Rev. 4/9/99

型号:	CS8101YDWFR20
是否Rohs认证：	不符合
生命周期：	Transferred
IHS 制造商：	CHERRY SEMICONDUCTOR CORP
包装说明：	SOIC-20
Reach Compliance Code：	unknown
风险等级：	5.75
Is Samacsys：	N
可调性：	FIXED
最大回动电压 1：	0.6 V
标称回动电压 1：	0.4 V
最大输入电压：	26 V
最小输入电压：	6 V
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0
最大电网调整率：	0.05%
最大负载调整率：	0.05%
功能数量：	1
输出次数：	1
端子数量：	20
工作温度TJ-Max：	150 °C
工作温度TJ-Min：	-40 °C
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流 1：	0.1 A
最大输出电压 1：	5.15 V
最小输出电压 1：	4.85 V
标称输出电压 1：	5 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TAPE AND REEL
认证状态：	Not Qualified
调节器类型：	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
子类别：	Other Regulators
表面贴装：	YES
技术：	BIPOLAR
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
最大电压容差：	3%
Base Number Matches：	1

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