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产品型号DAC7574IDGSR的概述

DAC7574IDGSR概述 DAC7574IDGSR是一款由德州仪器（Texas Instruments）生产的数字到模拟转换器（DAC）。这一芯片属于其DAC757x系列，具备高性能和低功耗的特性，适用于各种工业和消费类应用。DAC7574IDGSR能够将数字信号转换为对应的模拟电压信号，提供高达12位的分辨率，使其在需要高精度输出的场合极具竞争力。该芯片通过I²C接口进行数据通信，支持多种地址配置，支持多达八个DAC的级联配置。这使得DAC7574IDGSR在实施复杂的多通道信号处理系统时，特别值得考虑。此外，其流线型设计和小型封装使得DAC7574IDGSR在空间受限的应用中也能占据一席之地。 DAC7574IDGSR的适用领域广泛，包括但不限于以下几种应用：运动控制、自动化设备、工业过程控制、医疗设备以及消费类电子产品中的信号处理。这款DAC因其卓越的性能，已成为工程师在设计...

产品型号DAC7574IDGSR的Datasheet PDF文件预览

DAC7574

www.ti.com

SLAS375–JUNE 2003

QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT,

I²C INTERFACE DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

•

Micropower Operation: 600 µA at 5 V V_DD

Power-On Reset to Zero

+2.7 V to +5.5 V Analog Power Supply

12-Bit Monotonic

I²C™ Interface Up to 3.4 Mbps

The DAC7574 is a low-power, quad channel, 12-bit

buffered voltage output DAC. Its on-chip precision out-

put amplifier allows rail-to-rail output swing to be

achieved. The DAC7574 utilizes an I²C compatible two

wire serial interface supporting high-speed interface

mode with address support of up to four DAC7574s for

a total of 16 channels on the bus.

•

Data Transmit Capability

On-Chip Output Buffer Amplifier, Rail-to-Rail

Operation

Double-Buffered Input Register

Address Support for up to Four DAC7574s

The DAC7574 uses V_DDand GND to set the output

range of the DAC. The DAC7574 incorporates a

power-on-reset circuit that ensures that the DAC output

powers up at zero volts and remains there until a valid

write takes place to the device. The DAC7574 contains

a power-down feature, accessed via the internal control

device to 200 nA at 5 V.

•

Synchronous Update Support for up to 16

Channels

Operation From -40°C to 105°C

Small 10 Lead MSOP Package

•

The low power consumption of this part in normal

operation makes it ideally suited to portable battery

operated equipment. The power consumption is less

than 3mW at V_DD= 5 V reducing to 1 µW in power-down

mode.

APPLICATIONS

•

Process Control

•

Data Acquisition Systems

Closed-Loop Servo Control

PC Peripherals

The DAC7574 is available in a 10-lead MSOP package.

Portable Instrumentation

Data

Buffer A

DAC

DAC A

DAC D

OUT

Data

Buffer D

DAC

OUT

SCL

SDA

Power-Down

Control Logic

Buffer

Control

I C Block

Resistor

Network

GND

I2C is a trademark of Philips Corporation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily in-

cludetestingofallparameters.

DAC7574

www.ti.com

SLAS375–JUNE 2003

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT

PACKAGE

DRAWING

NUMBER

SPECIFICATION

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT MEDIA

DAC7574

10-MSOP

DGS

-40°C TO +105°C

D774

DAC7574IDGS

80 Piece Tube

DAC7574IDGSR

2500 Piece Tape and Reel

DGS PACKAGE

(TOPVIEW)

PIN DESCRIPTIONS

NAME

DESCRIPTION

Analog output voltage from DAC A

Analog output voltage from DAC B

V_OUT

GND

Ground reference point for all circuitry on the

part

V_DD

GND

DAC7574

7 SDA

6 SCL

V_OUTC

V_OUT

Analog output voltage from DAC C

Analog output voltage from DAC D

Serial clock input

V_OUTD

SCL

SDA

V_DD

Serial data input and output

Analog voltage supply input

Device address select - I²C

(1)

ABSOLUTE MAXIMUM RATINGS

V_DDto GND

–0.3 V to +6 V

–0.3 V to V_DD+ 0.3 V

– 40°C to +105°C

– 65°C to +150°C

+150°C

Digital input voltage to GND

V_OUTto GND

Operating temperature range

Storage temperature range

Junction temperature range (T_Jmax)

Power dissipation:

Thermal impedance (ΘJA)

Thermal impedance (ΘJC)

Vapor phase (60s)

270°C/W

77°C/W

Lead temperature, soldering:

215°C

Infrared (15s)

220°C

(1)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

DAC7574

www.ti.com

SLAS375–JUNE 2003

ELECTRICAL CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.

PARAMETER

(1)

TEST CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

Bits

LSB

Relative accuracy

Differential nonlinearity

Zero-scale error

Full-scale error

± 8

± 1

Specified monotonic by design

LSB

-0.15

±1.0

± 1.0

% of FSR

µV/°C

Gain error

Zero code error drift

±7

Gain temperature coefficient

± 3

ppm of

FSR/°C

(2)

OUTPUT CHARACTERISTICS

Output voltage range

V_DD

µs

Output voltage settling time (full scale)

R_L= ∞; 0 pF < C_L< 200 pF

R_L= ∞ ; C_L= 500 pF

µs

Slew rate

V/µs

LSB

DC crosstalk (channel-to-channel)

AC crosstalk (channel-to-channel)

Capacitive load stability

0.25

-100

470

1000

1 kHz Sine Wave

R_L= ∞

R_L= 2 kΩ

Digital-to-analog glitch impulse

1 LSB change around major

carry

nV-s

Digital feedthrough

DC output impedance

Short-circuit current

0.3

nV-s

Ω

V_DD= 5 V

V_DD= 3 V

2.5

µs

Power-up time

Coming out of power-down

mode, V_DD= +5 V

Coming out of power-down

mode, V_DD= +3 V

µs

(2)

LOGIC INPUTS

Input current

± 1

µA

V_{IN_L}, Input low voltage

V_{IN_H}, Input high voltage

Pin Capacitance

0.3xV_DD

V_DD= 3 V

0.7xV_DD

2.7

POWER REQUIREMENTS

V_DD

5.5

I_DD(normal operation), including reference current

I_DD@ V_DD=+3.6V to +5.5V

I_DD@ V_DD=+2.7V to +3.6V

I_DD(all power-down modes)

I_DD@ V_DD=+3.6V to +5.5V

I_DD@ V_DD=+2.7V to +3.6V

POWER EFFICIENCY

I_OUT/I_DD

Excluding load current

V_IH= V_DDand V_IL=GND

600

550

900

750

µA

V_IH= V_DDand V_IL=GND

0.2

µA

0.05

I_LOAD= 2 mA, V_DD= +5 V

93%

(1)

(2)

Linearity tested using a reduced code range of 48 to 4047; output unloaded.

Specified by design and characterization, not production tested.

DAC7574

www.ti.com

SLAS375–JUNE 2003

ELECTRICAL CHARACTERISTICS (continued)

V_DD= 2.7 V to 5.5 V, R_L= 2 kΩ to GND; C_L= 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified.

PARAMETER

TEMPERATURE RANGE

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Specified performance

-40

+105

°C

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, R_L= 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

Standard mode

MIN

TYP

MAX

UNITS

kHz

MHz

µs

100

400

3.4

Fast mode

f_SCL

SCL clock frequency

High-Speed Mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

1.7

4.7

Bus free time between a

STOP and START condition

t_BUF

Fast mode

1.3

µs

Standard mode

4.0

µs

Hold time (repeated) START

condition

t_HD; t_STA

Fast mode

600

High-speed mode

160

Standard mode

4.7

µs

Fast mode

1.3

µs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

160

320

4.0

µs

Fast mode

600

t_HIGH

High-Speed Mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

120

4.7

µs

Setup time for a repeated

START condition

t_SU; t_STA

Fast mode

600

High-speed mode

160

Standard mode

250

t_SU; t_DAT

Data setup time

Data hold time

Fast mode

100

High-speed mode

Standard mode

3.45

0.9

µs

Fast mode

µs

t_HD; t_DAT

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

20 × 0.1C_B

150

1000

300

Fast mode

t_RCL

Rise time of SCL signal

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

20 × 0.1C_B

1000

300

Rise time of SCL signal after

a repeated START condition

and after an acknowledge

BIT

Fast mode

t_RCL1

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

160

300

20 × 0.1C_B

Fast mode

t_FCL

Fall time of SCL signal

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

DAC7574

www.ti.com

SLAS375–JUNE 2003

TIMING CHARACTERISTICS (continued)

V_DD= 2.7 V to 5.5 V, R_L= 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

Standard mode

MIN

20 × 0.1C_B

TYP

MAX

1000

300

UNITS

Fast mode

t_RDA

Rise time of SDA signal

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

160

300

20 × 0.1C_B

Fast mode

t_FDA

Fall time of SDA signal

High-speed mode, C_B= 100 pF max

High-speed mode, C_B= 400 pF max

Standard mode

160

4.0

µs

Setup time for STOP con-

dition

t_SU; t_STO

Fast mode

600

High-speed mode

160

Capacitive load for SDA and

SCL

C_B

t_SP

400

Fast mode

High-speed mode

Standard mode

Fast mode

Pulse width of spike sup-

pressed

Noise margin at the HIGH

level for each connected de-

vice (including hysteresis)

V_NH

0.2 V_DD

0.1 V_DD

High-speed mode

Standard mode

Fast mode

Noise margin at the LOW

level for each connected de-

vice (including hysteresis)

V_NL

High-speed mode

DAC7574

www.ti.com

SLAS375–JUNE 2003

TYPICAL CHARACTERISTICS

At T_A= +25°C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

Channel A

= 5 V

Channel B

= 5 V

-2

-4

-6

-8

-2

-4

-6

-8

1.0

0.5

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

512 1024 1536 2048 2560 3072 3584

Digital Input Code

512 1024 1536 2048 2560 3072 3584

Digital Input Code

Figure 1.

Figure 2.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

Channel C

= 5 V

Channel D

= 5 V

-2

-4

-6

-8

-2

-4

-6

-8

1.0

0.5

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

512 1024 1536 2048 2560 3072 3584

Digital Input Code

512 1024 1536 2048 2560 3072 3584

Digital Input Code

Figure 3.

Figure 4.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

Channel A

= 2.7 V

Channel B

= 2.7 V

-2

-4

-6

-8

-2

-4

-6

-8

1.0

0.5

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

512 1024 1536 2048 2560 3072 3584

Digital Input Code

512 1024 1536 2048 2560 3072 3584

Digital Input Code

Figure 5.

Figure 6.

DAC7574

www.ti.com

SLAS375–JUNE 2003

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, unless otherwise noted.

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

Channel C

= 2.7 V

Channel D

= 2.7 V

-2

-4

-6

-8

-2

-4

-6

-8

1.0

0.5

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

512 1024 1536 2048 2560 3072 3584

Digital Input Code

512 1024 1536 2048 2560 3072 3584

Digital Input Code

Figure 7.

Figure 8.

ZERO-SCALE ERROR

vs TEMPERATURE

ZERO-SCALE ERROR

vs TEMPERATURE

= 5 V

= 2.7 V

CH A

CH C

CH D

CH B

-40

-10

-40

-10

- Free-Air Temperature - °C

Figure 9.

Figure 10.

FULL-SCALE ERROR

vs TEMPERATURE

FULL-SCALE ERROR

vs TEMPERATURE

= 5 V

= 2.7 V

CH C

CH A

CH C

CH D

CH A

CH D

CH B

-40

-10

-40

-10

- Free-Air Temperature - °C

Figure 11.

Figure 12.

DAC7574

www.ti.com

SLAS375–JUNE 2003

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, unless otherwise noted.

SINK CURRENT CAPABILITY

SOURCE CURRENT CAPABILITY

AT POSITIVE RAIL

AT NEGATIVE RAIL

0.150

5.50

5.45

5.40

5.35

5.30

Typical For All Channels

0.125

Typical For All Channels

0.100

0.075

0.050

0.025

0.000

= 2.7 V

= 5.5 V

DAC Loaded With FFF

DAC Loaded With 000

= 5.5 V

- Sink Current - mA

- Source Current - mA

SINK

SOURCE

Figure 13.

Figure 14.

SOURCE CURRENT CAPABILITY

AT POSITIVE RAIL

SUPPLY CURRENT

vs DIGITAL INPUT CODE

2.7

2.6

2.5

2.4

2.3

800

700

600

500

400

300

200

100

Typical For All Channels

= 5.5 V

= 2.7 V

DAC Loaded With FFF

All Channels Powered, No Load

= 2.7 V

512 1024 1536 2048 2560 3072 3584 4096

- Source Current - mA

SOURCE

Digital Input Code

Figure 15.

Figure 16.

SUPPLY CURRENT

vs TEMPERATURE

SUPPLY CURRENT

vs SUPPLY VOLTAGE

700

600

500

400

300

200

100

700

650

600

550

500

450

400

350

300

250

200

= 5.5 V

= 2.7 V

All Channels Powered, No Load

-10 20 50

All DACs Powered, No Load

-40

110

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

- Free-Air Temperature - °C

- Supply Voltage - V

Figure 17.

Figure 18.

DAC7574

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SLAS375–JUNE 2003

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, unless otherwise noted.

SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

1200

HISTOGRAM

OF CURRENT CONSUMPTION

2000

1500

1000

500

= 25°C

= 5 V

SCL Input (All Other Inputs = GND)

1000

800

600

400

200

= 5.5 V

= 2.7 V

500 520 540 560 580 600 620 640 660 680 700 720 740

Logic

- Logic Input Voltage - V

- Current Consumption - µA

Figure 19.

Figure 20.

HISTOGRAM

OF CURRENT CONSUMPTION

EXITING

POWER-DOWN MODE

2000

1500

1000

500

= 5 V

= 2.7 V

Powerup to Code 4000

-1

400 420 440 460 480 500 520 540 560 580 600 620

Time (2 µs/div)

- Current Consumption - µA

Figure 21.

Figure 22.

OUTPUT GLITCH (Mid-Scale)

OUTPUT GLITCH (Worst Case)

2.56

2.54

2.52

2.50

2.48

2.46

2.44

2.42

2.40

4.74

4.72

4.70

4.68

4.66

4.64

4.62

4.60

4.58

4.56

= 5 V

Code 7FF to 800 to 7FF

Code EFF to F00 to EFF

H H H

(Glitch Occurs Every N*256 Code

Boundary)

(Glitch Occurs Every N*256 Code Boundary)

Time (15 µs/div)

Figure 23.

Figure 24.

DAC7574

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SLAS375–JUNE 2003

TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, unless otherwise noted.

ABSOLUTE ERROR

= 5 V

= 25°C

= 2.7 V

Channel A Output

Channel B Output

T = 25°C

Channel A Output

Channel C Output

Channel B Output

Channel D Output

Channel C Output

-2

-6

Channel D Output

512 1024 1536 2048 2560 3072 3584

Digital Input Code

Figure 25.

Figure 26.

LARGE SIGNAL

SETTLING TIME

LARGE SIGNAL

SETTLING TIME

3.0

2.5

2.0

1.5

1.0

0.5

0.0

= 5 V

= 2.7 V

Output Loaded with

200 pF to GND

10% to 90% FSR

Output Loaded with

200 pF to GND

10% to 90% FSR

Time (25 µs/div)

Figure 27.

Figure 28.

DAC7574

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SLAS375–JUNE 2003

THEORY OF OPERATION

D/A SECTION

The architecture of the DAC7574 consists of a string DAC followed by an output buffer amplifier. Figure 29

shows a generalized block diagram of the DAC architecture.

50 kW

70 kW

Ref+

OUT

Resistor String

DAC Register

Ref-

GND

Figure 29. R-String DAC Architecture

The input coding to the DAC7574 is unsigned binary, which gives the ideal output voltage as:

4096

V_OUT+ V_DD

(1)

Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095.

RESISTOR STRING

The resistor string section is shown in Figure 30. It is basically a divide-by-2 resistor, followed by a string of

resistors, each of value R. The code loaded into the DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the

amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.

To Output

Amplifier

GND

Figure 30. Typical Resistor String

Output Amplifier

The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,

which gives an output range of 0V to V_DD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND.

The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs

with a half-scale settling time of 8 µs with the output unloaded.

I²C Interface

I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,

January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus

is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through

open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,

controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also

generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or

transmits data on the bus under control of the master device.

DAC7574

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SLAS375–JUNE 2003

THEORY OF OPERATION (continued)

The DAC7574 works as a slave and supports the following data transfer modes, as defined in the I²C-Bus

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data

transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in

this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as

H/S-mode. The DAC7574 supports 7-bit addressing; 10-bit addressing and general call address are not

supported.

F/S-Mode Protocol

•

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 31. All I²C-compatible devices should

recognize a start condition.

•

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 32). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 33) by pulling the SDA line low

during the entire high period of the 9^thSCL cycle. Upon detecting this acknowledge, the master knows that

communication link with a slave has been established.

•

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from

the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication link

with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a

stop condition, all devices know that the bus is released, and they wait for a start condition followed by a

matching address.

H/S-Mode Protocol

•

When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

The master generates a start condition followed by a valid serial byte containing H/S master code

00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to

acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to

support 3.4 Mbps operation.

•

The master then generates a repeated start condition (a repeated start condition has the same timing as the

start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that

transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the

internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated

start conditions should be used to secure the bus in H/S-mode.

DAC7574

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SLAS375–JUNE 2003

THEORY OF OPERATION (continued)

SDA

SCL

Start

Stop

Condition

Figure 31. START and STOP Conditions

SDA

SCL

Data Line

Stable;

Change of Data Allowed

Data Valid

Figure 32. Bit Transfer on the I²C Bus

Data Output

by Transmitter

Not Acknowledge

Data Output

by Receiver

Acknowledge

SCL From

Master

Clock Pulse for

Acknowledgement

START

Condition

Figure 33. Acknowledge on the I²C Bus

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Recognize START or

Recognize STOP or

REPEATED START

Condition

REPEATED START

Condition

Generate ACKNOWLEDGE

Signal

SDA

MSB

Acknowledgement

Signal From Slave

Address

R/W

SCL

3 - 8

ACK

Clock Line Held Low While

Interrupts are Serviced

START or

Repeated START

Condition

STOP or

Repeated START

Condition

Figure 34. Bus Protocol

DAC7574 I²C Update Sequence

The DAC7574 requires a start condition, a valid I²C address, a control byte, an MSB byte, and an LSB byte for a

single update. After the receipt of each byte, DAC7574 acknowledges by pulling the SDA line low during the high

period of a single clock pulse. A valid I²C address selects the DAC7574. The control byte sets the operational

mode of the selected DAC7574. Once the operational mode is selected by the control byte, DAC7574 expects an

MSB byte followed by an LSB byte for data update to occur. DAC7574 performs an update on the falling edge of

the acknowledge signal that follows the LSB byte.

Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte

continuously determine the type of update performed. Thus, for the first update, DAC7574 requires a start

condition, a valid I²C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,

DAC7574 needs an MSB byte and an LSB byte as long as the control command remains the same.

Using the I²C high-speed mode (f_scl= 3.4 MHz), the clock running at 3.4 MHz, each 12-bit DAC update other than

the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge

signal), at 188.88 KSPS. Using the fast mode (f_scl= 400 kHz), clock running at 400 kHz, maximum DAC update

rate is limited to 22.22 KSPS. Once a stop condition is received DAC7574 releases the I²C bus and awaits a new

start condition.

Address Byte

MSB

LSB

R/W

The address byte is the first byte received following the START condition from the master device. The first five

bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select

bits A1 and A0. The A1, A0 address inputs can be connected to V_DDor digital GND, or can be actively driven by

TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of

the DAC7574. Up to 4 devices (DAC7574) can still be connected to the same I²C-Bus.

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Broadcast Address Byte

MSB

LSB

Broadcast addressing is also supported by DAC7574. Broadcast addressing can be used for synchronously

updating or powering down multiple DAC7574 devices. DAC7574 is designed to work with other members of the

DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,

DAC7574 responds regardless of the states of the address pins. Broadcast is supported only in write mode

(Master writes to DAC7574).

Control Byte

MSB

LSB

Sel1

Sel0

PD0

Table 1. Control Register Bit Descriptions

Bit Name

Bit Number/Description

Load1 (Mode Select) Bit

Load0 (Mode Select) Bit

Are used for selecting the update mode.

Store I²C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the

temporary register of a selected channel. This mode does not change the DAC output of the selected

channel.

Update selected DAC with I²C data. Most commonly utilized mode. The contents of MS-BYTE and

LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of

the selected channel. This mode changes the DAC output of the selected channel with the new data.

4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information)

are stored in the temporary register and in the DAC register of the selected channel. Simultaneously,

the other three channels get updated with previously stored data from the temporary register. This

mode updates all four channels together.

Broadcast update mode. This mode has two functions. In broadcast mode, DAC7574 responds

regardless of local address matching, and channel selection becomes irrelevant as all channels update.

This mode is intended to enable up to 16 channels simultaneous update, if used with the I²C broadcast

address (1001 0000).

If Sel1=0

All four channels are updated with the contents of their temporary register

data.

If Sel1=1

All four channels are updated with the MS-BYTE and LS-BYTE data or

powerdown.

Sel1

Sel0

Buff Sel1 Bit

Channel Select Bits

Buff Sel0 Bit

Channel A

Channel B

Channel C

Channel D

PD0

Power Down Flag

Normal operation

Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2).

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Table 2. Control Byte

MSB7

MSB6

MSB5...

Don’t

Care

MSB

(PD1)

MSB-1

(PD2)

MSB-2

...LSB

Load1

Load0

Ch Sel 1 Ch Sel 0

PD0

DESCRIPTION

(Address

Select)

Write to temporary

data

Data

Write to temporary

data

Data

Write to temporary

data

Write to temporary

data

(00, 01, 10, or 11)

Write to TRx (selected

by C2 &C1

w/Powerdown Com-

mand

see Table 8

(00, 01, 10, or 11)

Write to TRx (selected

by C2 &C1 and load

DACx w/data

Data

Power-down DACx

(selected by C2 and

C1)

see Table 8

Write to TRx (selected

by C2 &C1 w/ data and

load all DACs

Data

Power-down DACx

(selected by C2 and

C1) & load all DACs

see Table 8

Broadcast Modes (controls up to 4 devices on a single serial bus)

Update all DACs, all

devices with previously

stored TRx data

Update all DACs, all

devices with MSB[7:0]

and LSB[7:0] data

Data

Power-down all DACs,

all devices

see Table 8

Most Significant Byte

Most Significant Byte MSB[7:0] consists of eight most significant bits of 12-bit unsigned binary D/A conversion

data. C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8.

Least Significant Byte

Least Significant Byte LSB[7:0] consists of the 4 least significant bits of the 12-bit unsigned binary D/A

conversion data, followed by 4 don’t care bits. DAC7574 updates at the falling edge of the acknowledge signal

that follows the LSB[0] bit.

Default Readback Condition

If the user initiates a readback of a specified channel without first writing data to that specified channel, the

default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.

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LDAC Functionality

Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal

that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the

channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four

DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only

be used after the buffers temporary registers are properly updated through software.

DAC7574 Registers

Table 3. DAC7574 Architecture Register Descriptions

Description

CTRL[7:0]

Stores 8-bit wide control byte sent by the master

Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit

power-down data.

MSB[7:0]

LSB[7:0]

Stores the 4 least significant bits of unsigned binary data sent by the master.

TRA[13:0], TRB[13:0],

TRC[13:0], TRD[13:0]

14-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 12

LSBs store data.

DRA[13:0], DRB[13:0],

DRC[13:0], DRD[13:0]

14-bit DAC registers for each channel. Two MSBs store power-down information, 12 LSBs store DAC data.

An update of this register means a DAC update with data or power-down.

DAC7574 as a Slave Receiver - Standard and Fast Mode

Figure 35 shows the standard and fast mode master transmitter addressing a DAC7574 Slave Receiver with a

7-bit address.

SLAVE ADDRESS R/W

Ctrl-Byte

MS-Byte

LS-Byte A/A

Data Transferred

(n* Words + Acknowledge)

Word = 12 Bit

”0” (write)

From Master to DAC7574

DAC7574 I C-SLAVE ADDRESS:

MSB

LSB

From DAC7574 to Master

A = Acknowledge (SDA LOW)

A0 R/W

A = Not Acknowledge (SDA HIGH)

S = START Condition

‘0’ = Write to DAC7574

‘1’ = Read from DAC7574

Factory Preset

Sr = Repeated START Condition

P = STOP Condition

A0 = I C Address Pin

A1 = I C Address Pin

Figure 35. Standard and Fast Mode: Slave Receiver

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DAC7574 as a Slave Receiver - High-Speed Mode

Figure 36 shows the high-speed mode master transmitter addressing a DAC7574 Slave Receiver with a 7-bit

address.

F/S-Mode

HS-Mode

Ctrl-Byte

F/S-Mode

HS-Master Code

Sr Slave Address R/W

MS-Byte

LS-Byte A/A

Data Transferred

(n* Words + Acknowledge)

Word = 12 Bit

”0” (write)

HS-Mode Continues

Sr Slave Address

HS-Mode Master Code:

MSB

LSB

Control Byte:

MSB

R/X

LSB

Sel1 Sel2 PD0

MS-Byte:

MSB

Load1 (Mode Select) Bit

Load0 (Mode Select) Bit

LSB

D11 D10 D9

Sel1 = Buff Sel1 (Channel) Select Bit

Sel0 = Buff Sel0 (Channel) Select Bit

PD0 = Power Down Flag

LS-Byte:

MSB

LSB

= Don’t Care

D11 - D0 = Data Bits

Figure 36. High-Speed Mode: Slave Receiver

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Master Transmitter Writing to a Slave Receiver (DAC7574) in Standard/Fast Modes

All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This

control byte specifies the operation mode of DAC7574 and determines which channel of DAC7574 is being

accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the

following data is power-down data or regular data.

With (PD0-Bit = 0) the DAC7574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE –

HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I²C-Bus is

recognized (refer to the DATA INPUT MODE section of Table 4).

With (PD0-Bit = 1) the DAC7574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN

MODE section of Table 4).

Table 4. Write Sequence in F/S Mode

DATA INPUT MODE

Transmitter

Master

MSB

LSB Comment

Begin sequence

Start

Master

R/W Write addressing (R/W=0)

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

DAC7574 Acknowledges

D8 D7 D6

DAC7574 Acknowledges

Load 1

PD0 Control byte (PD0=0)

DAC7574

Master

D11

D10

Writing data word, high byte

Writing data word, low byte

DAC7574

Master

DAC7574

Master

(1)

(2)

Data or done

Data or Stop or Repeated Start

POWER DOWN MODE

Transmitter

Master

MSB

LSB Comment

Start

Begin sequence

Master

R/W Write addressing (R/W=0)

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

DAC7574 Acknowledges

Load 1

PD0 Control byte (PD0 = 1)

DAC7574

Master

PD1

PD2

Writing data word, high byte

Writing data word, low byte

Done

DAC7574

Master

DAC7574 Acknowledges

DAC7574

Master

DAC7574 Acknowledges

(1)

Stop or Repeated Start

(1)

(2)

Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.

Once DAC7574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP

condition or repeated START condition is received.

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Master Transmitter Writing to a Slave Receiver (DAC7574) in HS Mode

When writing data to the DAC7574 in HS-mode, the master begins to transmit what is called the HS-Master

Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master

Code is followed by a NOT acknowledge.

The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with

R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed by

the control byte, which is also acknowledged by the DAC7574. The LSB of the control byte (PD0-Bit) determines

if the following data is power-down data or regular data.

With (PD0-Bit = 0) the DAC7574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE –

HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I²C-Bus is recognized

(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).

With (PD0-Bit = 1) the DAC7574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE

WRITE SEQUENCE - POWER DOWN).

Table 5. Master Transmitter Writes to Slave Receiver (DAC7574) in HS-Mode

HS MODE WRITE SEQUENCE - DATA

Transmitter

Master

MSB

LSB Comment

Begin sequence

Start

Master

HS Mode Master Code

No device may acknowledge HS mas-

ter code

NONE

Not Acknowledge

Master

Repeated Start

Master

Load 1

R/W Write addressing (R/W=0)

PD0 Control byte (PD0=0)

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

DAC7574 Acknowledges

D8 D7 D6

DAC7574 Acknowledges

DAC7574

Master

D11

D10

Writing data word, MSB

Writing data word, LSB

DAC7574

Master

DAC7574

Master

(1)

(2)

Data or done

Data or Stop or Repeated Start

HS MODE WRITE SEQUENCE - POWER DOWN

Transmitter

Master

MSB

LSB Comment

Start

Begin sequence

Master

HS Mode Master Code

No device may acknowledge HS mas-

ter code

NONE

Not Acknowledge

Repeated Start

Master

DAC7574 Acknowledges

Load 2 Buff Sel 1 Buff Sel 0

DAC7574 Acknowledges

R/W Write addressing (R/W = 0)

PD0 Control Byte (PD0=1)

DAC7574

Master

Load 1

DAC7574

Master

PD1

PD2

Writing data word, high byte

Writing data word, low byte

Done

DAC7574

Master

DAC7574 Acknowledges

DAC7574

Master

DAC7574 Acknowledges

(1)

Stop or repeated start

(1)

(2)

Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.

Once DAC7574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start

condition is received.

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DAC7574 as a Slave Transmitter - Standard and Fast Mode

Figure 37 shows the standard and fast mode master transmitter addressing a DAC7574 Slave Transmitter with a

7-bit address.

(DAC7574)

(MASTER)

(DAC7574)

SLAVE ADDRESS R/W Ctrl <7:1> PD0

Sr Slave Address R/W

MS-Byte

LS-Byte

A P

’1’ (read)

’0’ (write)

Data Transferred

(2 Bytes + Acknowledge)

(DAC7574) (MASTER) (MASTER)

Sr Slave Address R/W PDN-Byte MS-Byte A LS-Byte

’1’ (read)

’0’ = (Normal Mode)

(MASTER)

PD0

A P

’1’ = (Power Down Flag)

Data Transferred

(3 Bytes + Acknowledge)

PDN-Byte:

MSB

LSB

PD1 PD2

PD1 = Power-Down Bit

PD2 = Power-Down Bit

Figure 37. Standard and Fast Mode: Slave Transmitter

DAC7574 as a Slave Transmitter - High-Speed Mode

Figure 38 shows an I²C-Master addressing DAC7574 in high-speed mode (with a 7-bit address), as a Slave

Transmitter.

F/S-Mode

HS-Master Code

HS-Mode

(DAC7574)

(DAC7574) (MASTER) (MASTER)

Slave Address

R/W

Ctrl <7:1> PD0 A Sr Slave Address R/W

MS-Byte

LS-Byte

’1’ (read)

’0’ (write)

Data Transferred

(2 Bytes + Acknowledge)

’0’ = (Normal Mode)

(DAC7574)

Sr Slave Address R/W PDN-Byte

’1’ (read)

(MASTER)

(MASTER) (MASTER)

PD0

MS-Byte A LS-Byte A P

’1’ = (Power -Down Flag)

Data Transferred

(3 Bytes + Acknowledge)

Figure 38. High-Speed Mode: Slave Transmitter

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Master Receiver Reading From a Slave Transmitter (DAC7574) in Standard/Fast Modes

When reading data back from the DAC7574, the user begins with an address byte (with R/W = 0) after which the

DAC7574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which

is also acknowledged by the DAC7574. Following this there is a REPEATED START condition by the Master and

the address is resent with (R/W = 1). This is acknowledged by the DAC7574, indicating that it is prepared to

transmit data. Two or three bytes of data are then read back from the DAC7574, depending on the (PD0-Bit).

The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.

With the (PD0-Bit = 0) the DAC7574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to

Table 2. Data Readback Mode - 2 bytes).

With the (PD0-Bit = 1) the DAC7574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the

HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).

Table 6. Read Sequence in F/S Mode

DATA READBACK MODE - 2 BYTES

Transmitter

Master

MSB

LSB

R/W

PD0

Comment

Start

Begin sequence

Write addressing (R/W=0)

Master

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

Load 1

Control byte (PD0=0)

DAC7574

Master

DAC7574 Acknowledges

Repeated Start

Master

R/W

Read addressing (R/W = 1)

DAC7574

Master

DAC7574 Acknowledges

D8 D7

Master Acknowledges

Master Not Acknowledges

(1)

D11

D10

Reading data word, high byte

DAC7574

Master

Reading data word, low byte

Master signal end of read

Done

Master

Stop or Repeated Start

DATA READBACK MODE - 3 BYTES

Transmitter

Master

MSB

LSB

R/W

PD0

Comment

Start

Begin sequence

Write addressing (R/W=0)

Master

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

Load 1

Control byte (PD0=1)

DAC7574

Master

DAC7574 Acknowledges

Repeated Start

Master

R/W

Read addressing (R/W = 1)

Read power down byte

DAC7574

Master

DAC7574 Acknowledges

PD1

D11

PD2

D10

Master Acknowledges

D8 D7

Master Acknowledges

Master Not Acknowledges

(1)

DAC7574

Master

Reading data word, high byte

DAC7574

Master

Reading data word, low byte

Master signal end of read

Done

Master

Stop or Repeated Start

(1)

Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.

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Master Receiver Reading From a Slave Transmitter (DAC7574) in HS-Mode

When reading data to the DAC7574 in HS-MODE, the master begins to transmit, what is called the HS-Master

Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master

Code is followed by a NOT acknowledge.

The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte

(with R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed

by the control byte, which is also acknowledged by the DAC7574.

Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).

This is acknowledged by the DAC7574, indicating that it is prepared to transmit data. Two or Three bytes of data

are then read back from the DAC7574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0

determines, which channel data is read back. A STOP condition follows.

With the (PD0-Bit = 0) the DAC7574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to

Table 7 HS-Mode Readback Sequence).

With the (PD0-Bit = 1) the DAC7574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the

HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).

Table 7. Master Receiver Reading Slave Transmitter (DAC7574) in HS-Mode

HS MODE READBACK SEQUENCE

Transmitter

Master

MSB

Start

LSB

Comment

Begin sequence

Master

HS Mode Master Code

No device may acknowledge HS

master code

NONE

Not Acknowledge

Master

Repeated Start

R/W

PD0

Write addressing (R/W=0)

Control byte (PD0 = 1)

DAC7574

Master

DAC7574 Acknowledges

Load 0 Buff Sel 1 Buff Sel 0

Load 1

DAC7574

Master

DAC7574 Acknowledges

Repeated Start

Master

R/W

Read addressing (R/W=1)

Power-down byte

DAC7574

Master

DAC7574 Acknowledges

PD1

D11

PD2

D10

Master Acknowledges

D8 D7 D6

Master Acknowledges

DAC7574

Master

Reading data word, high byte

DAC7574

Master

Reading data word, low byte

Master signal end of read

Done

Master Not Acknowledges

Stop or Repeated Start

Master

Power-On Reset

The DAC7574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,

the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is

made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC

while it is in the process of powering up. No device pin should be brought high before supply is applied.

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Power-Down Modes

The DAC7574 contains four separate power-down modes of operation. The modes are programmable via two

most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits

correspond to the mode of operation of the device.

Table 8. Power-Down Modes of Operation for the DAC7574

CTRL[0]

MSB[7]

MSB[6]

OPERATING MODE

High Impedance Output

1 kΩ to GND

100 kΩ to GND

High Impedance

When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per

channel. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not

only does the supply current fall but also the output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the advantage that the output impedance of the device

is known while in power-down mode. There are three different options: The output is connected internally to GND

through a 1 kΩ resistor, a 100 kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in

Figure 39.

Amplifier

Resistor

OUT

String DAC

Powerdown

Circuitry

Resistor

Network

Figure 39. Output Stage During Power Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC

µs for V_DD= 3 V. (See the Typical Curves section for additional information.)

The DAC7574 offers a flexible power-down interface based on channel register operation. A channel consists of

a single 12 bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR

and DR are both 14 bits wide. Two MSBs represent the power-down condition and the 12 LSBs represent data

for TR and DR. By using bits 13 and 14 of TR and DR, a power-down condition can be temporarily stored and

used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[13] and TR[12] (DR[13]

and DR[12]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC7574 treats power-down

conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a

power-down condition to all the DAC7574s in the system, or it is possible to simultaneously power down a

channel while updating data on other channels.

CURRENT CONSUMPTION

The DAC7574 typically consumes 150µA at V_DD= 5 V and 125µA at V_DD= 3 V for each active channel, including

reference current consumption. Additional current consumption can occur at the digital inputs if V_IH<< V_DD. For

most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In

power-down mode, typical current consumption is 200 nA. A delay time of 10 to 20 ms after a power-down

command is issued to the DAC is typically sufficient for the power-down current to drop below 10 µA.

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DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC7574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset

and gain error margins, the DAC7574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2

kΩ can be driven by the DAC7574 while achieving a typical load regulation of 1%. As the load resistance drops

below 2 kΩ, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under

resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this

occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within

approximately the top 20 mV of the DAC’s digital input-to-voltage output transfer characteristic. The reference

voltage applied to the DAC7574 may be reduced below the supply voltage applied to V_DDin order to eliminate

this condition if good linearity is a requirement at full scale (under resistive loading conditions).

CROSSTALK

The DAC7574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low

crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel

is typically less than 0.5 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at

one channel, and measured at the remaining output channel) is typically under -100 dB.

OUTPUT VOLTAGE STABILITY

The DAC7574 exhibits excellent temperature stability of ±3 ppm/°C typical output voltage drift over the specified

temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window

for a ±1°C ambient temperature change. Combined with good dc noise performance and true 12-bit differential

linearity, the DAC7574 becomes a perfect choice for closed-loop control applications.

SETTLING TIME AND OUTPUT GLITCH PERFORMANCE

Settling time to within the 12-bit accurate range of the DAC7574 is achievable within 10 µs for a full-scale code

change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The

high-speed serial interface of the DAC7574 is designed in order to support up to 188ksps update rate. For

full-scale output swings, the output stage of each DAC7574 channel typically exhibits less than 100 mV of

overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely

low (~10 µV) given that the code-to-code transition does not cross an Nx256 code boundary. Due to internal

segmentation of the DAC7574, code-to-code glitches occur at each crossing of an Nx256 code boundary. These

glitches can approach 100 mVs for N = 15, but settle out within ~2 µs. Sufficient bypass capacitance is required

to ensure 10 µs settling under capacitive loading. To observe the settling performance under resistive load

conditions, the power supply (hence DAC7574 reference supply) must settle quicker than the DAC7574.

DAC7574

www.ti.com

SLAS375–JUNE 2003

APPLICATION INFORMATION

The following sections give example circuits and tips for using the DAC7574 in various applications. For more

information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.

BASIC CONNNECTIONS

For many applications, connecting the DAC7574 is extremely simple. A basic connection diagram for the

DAC7574 is shown in Figure 40. The 0.1 µF bypass capacitors help provide the momentary bursts of extra

current needed from the supplies.

DAC7574

OUT

GND

OUT

SDA

I C Pullup Resistors

1 kΩ to 10 kΩ (typical)

OUT

SCL

Microcontroller or

Microprocessor With

I C Port

SCL

SDA

NOTE: DAC7574 power and input/output connections are omitted for clarity, except I C Inputs.

Figure 40. Typical DAC7574 Connections

The DAC7574 interfaces directly to standard mode, fast mode and high-speed mode I²C controllers. Any

microcontroller’s I²C peripheral, including master-only and non-multiple-master I²C peripherals, work with the

DAC7574. The DAC7574 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not

necessary to provide for this unless other devices are on the same I²C bus.

Pullup resistors are necessary on both the SDA and SCL lines because I²C bus drivers are open-drain. The size

of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value

resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value

resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher

capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus

drivers may not be able to pull the bus line low.

USING GPIO PORTS FOR I²C

Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or

outputs. If an I²C controller is not available, the DAC7574 can be connected to GPIO pins, and the I²C bus

protocol simulated, or bit-banged, in software. An example of this for a single DAC7574 is shown in Figure 41.

DAC7574

www.ti.com

SLAS375–JUNE 2003

APPLICATION INFORMATION (continued)

DAC7574

OUT

SDA

SCL

GND

V C

OUT

V D

OUT

Microcontroller or

Microprocessor

GPIO-1

GPIO-2

NOTE: DAC7574 power and input/output connections are omitted for clarity, except I C Inputs.

Figure 41. Using GPIO With a Single DAC7574

Bit-banging I²C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and

output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line

go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is

pulling the line low, this reads as a zero in the port’s input register.

Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The

microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this

because the DAC7574 never drives its clock line low. This technique can also be used with multiple devices, and

has the advantage of lower current consumption due to the absence of a resistive pullup.

If there are any devices on the bus that may drive their clock lines low, the above method should not be used.

The SCL line should be high-Z or zero, and a pullup resistor provided as usual. Note also that this cannot be

done on the SDA line in any case, because the DAC7574 drives the SDA line low from time to time, as all I²C

devices do.

Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these

can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some

microcontrollers, but usually these are too weak for I²C communication. Test any circuit before committing it to

production.

DAC7574

www.ti.com

SLAS375–JUNE 2003

APPLICATION INFORMATION (continued)

POWER SUPPLY REJECTION

The positive reference voltage input of DAC7574 is internally tied to the power supply pin of the device. This

increases I²C system flexibility, creating room for an extra I²C address pin in a low pin-count package. To

eliminate the supply noise appearing at the DAC output, the user must pay close attention to how DAC7574 is

powered. The supply to DAC7574 must be clean and well regulated. For best performance, use of a precision

voltage reference is recommended to supply power to DAC7574. This is equivalent to providing a precision

external reference to the device. Due to low power consumption of DAC7574, load regulation errors are

negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of DAC7574, the precision

reference voltage should be close to the I²C bus pullup voltage. For 3-V, 3.3-V and 5-V I²C bus pullup voltages,

REF2930, REF2933 and REF02 precision voltage references are recommended respectively. These precision

voltage references can be used to supply power for multiple devices on a system.

USING REF02 AS A POWER SUPPLY FOR DAC7574

Due to the extremely low supply current required by the DAC7574, a possible configuration is to use a REF02

+5 V precision voltage reference to supply the required voltage to the DAC7574’s supply input as well as the

reference input, as shown in Figure 42. This is especially useful if the power supply is quite noisy or if the system

supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC7574.

If the REF02 is used, the current it needs to supply to the DAC7574 is 600 µA typical and 900 µA max for

V_DD= 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total

typical current required (with a 5-kΩ load on a single DAC output) is:

600 µA + (5 V / 5 kΩ) = 1.6 mA

The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400µV for 1.6-mA of current

drawn from it. This corresponds to a 0.33 LSB error for a 0 V to 5 V output range.

15 V

5 V

REF02

1.6 mA

SCL

SDA

I C

OUT

= 0 V to 5 V

Interface

DAC7574

Figure 42. REF02 Power Supply

LAYOUT

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power

supplies.

The power applied to V_DDshould be well-regulated and low noise. Switching power supplies and dc/dc

converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital

components can create similar high-frequency spikes as their internal logic switches states. This noise can easily

couple into the DAC output voltage through various paths between the power connections and analog output.

DAC7574

www.ti.com

SLAS375–JUNE 2003

As with the GND connection, V_DDshould be connected to a positive power-supply plane or trace that is separate

from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 µF to 10 µF

capacitor in parallel with a 0.1 µF bypass capacitor is strongly recommended. In some situations, additional

bypassing may be required, such as a 100 µF electrolytic capacitor or even a Pi filter made up of inductors and

capacitors—all designed to essentially low-pass filter the –5 V supply, removing the high-frequency noise.

PACKAGE OPTION ADDENDUM

www.ti.com

3-Mar-2013

PACKAGING INFORMATION

Orderable Device

DAC7574IDGS

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

VSSOP

DGS

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

-40 to 105 D774

DAC7574IDGSG4

DAC7574IDGSR

DAC7574IDGSRG4

ACTIVE

DGS

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

2500

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-Mar-2013

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

DAC7574IDGSR

VSSOP

DGS

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Nov-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSSOP DGS 10

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

DAC7574IDGSR

2500

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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DAC7574IDGSR产品参数

型号:	DAC7574IDGSR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	MSOP
包装说明：	TSSOP, TSSOP10,.19,20
针数：	10
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.19
Is Samacsys：	N
最大模拟输出电压：	5.5 V
最小模拟输出电压：
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	S-PDSO-G10
JESD-609代码：	e4
长度：	3 mm
最大线性误差 (EL)：	0.1953%
湿度敏感等级：	2
位数：	12
功能数量：	1
端子数量：	10
最高工作温度：	105 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP10,.19,20
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
采样速率：	0.043 MHz
座面最大高度：	1.07 mm
最大稳定时间：	10 µs
标称安定时间 (tstl)：	10 µs
子类别：	Other Converters
最大压摆率：	0.9 mA
标称供电电压：	3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
Base Number Matches：	1

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