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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • DRV8711DCPR
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  • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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  • 深圳市富科达科技有限公司

     该会员已使用本站13年以上
  • DRV8711DCPR 现货库存
  • 数量11518 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号22+ 
  • 全新原装进口现货特价热卖,长期供货
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    QQ:1220223788QQ:1220223788 复制
  • 0755-28767101 QQ:1327510916QQ:1220223788
  • DRV8711DCPR图
  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR 现货库存
  • 数量22000 
  • 厂家TI【原装正品】 
  • 封装HTSSOP38 
  • 批号▊ NEW ▊ 
  • ▊▊★代理TI▊▊全系列销售【100%全新原装正品】★长期供应,量大可订,价格优惠!
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  • 0755-23125986 QQ:1551106297QQ:3059638860
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  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • DRV8711DCPR 现货库存
  • 数量9868 
  • 厂家TI 
  • 封装HTSSOP 
  • 批号24+ 
  • 全新原装,特价,假一罚十
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  • 0755-89587732 QQ:354696650QQ:2850471056
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  • 集好芯城

     该会员已使用本站13年以上
  • DRV8711DCPR 现货库存
  • 数量16629 
  • 厂家TI(德州仪器) 
  • 封装 
  • 批号22+ 
  • 原装原厂现货
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  • 0755-83239307 QQ:3008092965QQ:3008092965
  • DRV8711DCPR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • DRV8711DCPR 现货库存
  • 数量9810 
  • 厂家TI 
  • 封装HTSSOP-38 
  • 批号25+ 
  • 只做原装正品现货销售
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  • 0755-82723761 QQ:867789136QQ:1245773710
  • DRV8711DCPR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • DRV8711DCPR 现货库存
  • 数量3000 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号25+ 
  • 原装正品特价销售
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    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • DRV8711DCPR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR 现货库存
  • 数量2000 
  • 厂家TI 
  • 封装HTSSOP (DCP) 
  • 批号新批次 
  • 新到现货、一手货源、当天发货、bom配单
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  • 深圳市华来深电子有限公司

     该会员已使用本站13年以上
  • DRV8711DCPR 现货库存
  • 数量8560 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号20+ 
  • 受权代理!全新原装现货特价热卖!
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    QQ:876098337QQ:876098337 复制
  • 0755-83238902 QQ:1258645397QQ:876098337
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  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • DRV8711DCPR 现货库存
  • 数量32560 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号2024+ 
  • 【原装优势★★★绝对有货】
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  • 0755-22968359 QQ:409801605
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  • 诚信溢美电子科技有限公司

     该会员已使用本站2年以上
  • DRV8711DCPR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号22+ 
  • 支持实单? 只做原装正品
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  • -0735-16670525391 QQ:1721899461
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • DRV8711DCPR 现货库存
  • 数量55000 
  • 厂家TI/德州仪器 
  • 封装HTSSOP38 
  • 批号24+ 
  • 原装正品原盒原标签
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  • 0755-82702619 QQ:2103443489QQ:2924695115
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  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • DRV8711DCPR 现货库存
  • 数量23200 
  • 厂家TI 
  • 封装N/A 
  • 批号21+ 
  • 全新原装有现货库存--价格有优势
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  • 0755-88601327 QQ:444961496QQ:2824256784
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  • 深圳市恒嘉威智能科技有限公司

     该会员已使用本站7年以上
  • DRV8711DCPR 现货库存
  • 数量12578 
  • 厂家TI/德州仪器 
  • 封装HTSSOP38 
  • 批号21+ 
  • 原装恒嘉威价格最实在
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    QQ:2274045202QQ:2274045202 复制
  • -0755-23942980 QQ:1036846627QQ:2274045202
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  • 润集微科技(杭州)有限公司

     该会员已使用本站2年以上
  • DRV8711DCPR 现货热卖
  • 数量10000 
  • 厂家TI 
  • 封装HTSSOP-38 
  • 批号2022+ 
  • 全新原装正品现货,欢迎来电咨询!
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    QQ:652208235QQ:652208235 复制
  • 0571-81022721 QQ:2361757982QQ:652208235
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  • 深圳市励创源科技有限公司

     该会员已使用本站2年以上
  • DRV8711DCPR 优势库存
  • 数量35600 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号21+ 
  • 诚信经营,原装现货,假一赔十,欢迎咨询15323859243
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  • -0755-82711370 QQ:815442201QQ:483601579
  • DRV8711DCPR图
  • 润集微科技(杭州)有限公司

     该会员已使用本站2年以上
  • DRV8711DCPR 优势库存
  • 数量10000 
  • 厂家TI 
  • 封装HTSSOP-38 
  • 批号2022+ 
  • 全新原装正品现货,欢迎来电咨询!
  • QQ:2361757982QQ:2361757982 复制
    QQ:652208235QQ:652208235 复制
  • 0571-81022721 QQ:2361757982QQ:652208235
  • DRV8711DCPR图
  • 润集微科技(杭州)有限公司

     该会员已使用本站2年以上
  • DRV8711DCPR 热卖库存
  • 数量10000 
  • 厂家TI 
  • 封装HTSSOP-38 
  • 批号2022+ 
  • 全新原装正品现货,欢迎来电咨询!
  • QQ:2361757982QQ:2361757982 复制
    QQ:652208235QQ:652208235 复制
  • 0571-81022721 QQ:2361757982QQ:652208235
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  • 深圳市裕诚科通电子有限公司

     该会员已使用本站1年以上
  • DRV8711DCPR 热卖库存
  • 数量2500 
  • 厂家TI/德州仪器 
  • 封装HTSSOP38 
  • 批号2130+ 
  • 2000/卷原裝正品真实库存假一罚十
  • QQ:2885765644QQ:2885765644 复制
  • 00755-83776933 QQ:2885765644
  • DRV8711DCPR图
  • 深圳市拓森弘电子有限公司

     该会员已使用本站1年以上
  • DRV8711DCPR
  • 数量5000 
  • 厂家TI/德州仪器 
  • 封装VQFN32 
  • 批号21+ 
  • 原厂原包装,库存现货实报
  • QQ:1300774727QQ:1300774727 复制
  • 13714410484 QQ:1300774727
  • DRV8711DCPR图
  • 深圳市昌和盛利电子有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR
  • 数量28650 
  • 厂家TI【原装正品】 
  • 封装HTSSOP38 
  • 批号▊ NEW ▊ 
  • ▊▊★代理TI全系列销售【100%全新原装正品】★长期供应,量大可订,价格优惠!
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    QQ:3059638860QQ:3059638860 复制
  • 0755-23125986 QQ:1551106297QQ:3059638860
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR
  • 数量12048 
  • 厂家TI(德州仪器) 
  • 封装HTSSOP38 
  • 批号23+ 
  • 原厂可订货,技术支持,直接渠道。可签保供合同
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  • 0755-83061789 QQ:3007947087QQ:3007947087
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  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • DRV8711DCPR
  • 数量10020 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号24+ 
  • 原装现货
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
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  • 深圳市捷立辉科技有限公司

     该会员已使用本站10年以上
  • DRV8711DCPR
  • 数量69896 
  • 厂家TI/德州仪器 
  • 封装HSOP38 
  • 批号21+ 
  • 绝对原装现货,公司真实库存
  • QQ:1803576909QQ:1803576909 复制
  • -0755-82792948 QQ:1803576909
  • DRV8711DCPR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR
  • 数量2000 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 优势代理渠道,原装正品,可全系列订货开增值税票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
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  • 深圳市亿智腾科技有限公司

     该会员已使用本站8年以上
  • DRV8711DCPR
  • 数量16680 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号16+ 
  • 假一赔十★全新原装现货★★特价供应★工厂客户可放款
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  • 0755-82566711 QQ:799387964QQ:2777237833
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  • 北京云中青城科技有限公司

     该会员已使用本站8年以上
  • DRV8711DCPR
  • 数量300 
  • 厂家TI 
  • 封装 
  • 批号20+ 
  • 不是原装不要钱,可含税
  • QQ:1290208342QQ:1290208342 复制
    QQ:260779663QQ:260779663 复制
  • 010-62669145 QQ:1290208342QQ:260779663
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  • 深圳市鹏和科技有限公司

     该会员已使用本站16年以上
  • DRV8711DCPR
  • 数量582 
  • 厂家TI 
  • 封装HTSSOP 
  • 批号23+ 
  • 原装正品 代理渠道
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  • 755-83990319 QQ:3004290789QQ:3004290786
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  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • DRV8711DCPR
  • 数量66002 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
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  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
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  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR
  • 数量5800 
  • 厂家TI(德州仪器) 
  • 封装38-TFSOP(0.173,4.40mm 宽)裸露焊盘 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
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  • 18565729389 QQ:3354557638QQ:3354557638
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  • 集好芯城

     该会员已使用本站13年以上
  • DRV8711DCPR
  • 数量19005 
  • 厂家TI/德州仪器 
  • 封装HTSSOP38 
  • 批号最新批次 
  • 原装原厂 现货现卖
  • QQ:3008092965QQ:3008092965 复制
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  • 0755-83239307 QQ:3008092965QQ:3008092965
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • DRV8711DCPR
  • 数量18019 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507168QQ:2355507168 复制
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  • 86-755-83219286 QQ:2355507168QQ:2355507169
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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • DRV8711DCPR
  • 数量44300 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号2019+ 
  • TI一级代理专营品牌绝对进口原装假一赔十
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  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
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  • 深圳市湘达电子有限公司

     该会员已使用本站10年以上
  • DRV8711DCPR
  • 数量3300 
  • 厂家TI/德州仪器 
  • 封装HTSSOP38 
  • 批号2020+ 
  • 全新原装现货,一片也是批量价。
  • QQ:215672808QQ:215672808 复制
  • 0755-83229772 QQ:215672808
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  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • DRV8711DCPR
  • 数量3000 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号25+ 
  • 原装正品长期供货
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • DRV8711DCPR
  • 数量3715 
  • 厂家TI 
  • 封装38-TFSOP(0.173,4.40mm 宽)裸露焊盘 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
  • QQ:2881894393QQ:2881894393 复制
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  • 0755- QQ:2881894393QQ:2881894392
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  • 深圳市晶美隆科技有限公司

     该会员已使用本站15年以上
  • DRV8711DCPR
  • 数量19800 
  • 厂家TI/德州仪器 
  • 封装HTSSOP28 
  • 批号24+ 
  • 假一罚十,原装进口正品现货供应,价格优势。
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  • 0755-82865294 QQ:198857245
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  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • DRV8711DCPR
  • 数量5600 
  • 厂家TI 
  • 封装HTSSOP38 
  • 批号23+ 
  • 100%深圳原装现货库存
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  • 18929336553 QQ:2276916927QQ:1977615742

产品型号DRV8711DCPR的概述

芯片DRV8711DCPR的概述 DRV8711DCPR是一款专为步进电机驱动应用设计的高性能驱动芯片,它由德州仪器(Texas Instruments)公司生产。该芯片不仅支持多种控制模式,如微步控制,还具备低功耗、高效率等特点,从而在工业自动化、3D打印机、机器人和其他驱动应用中得到了广泛应用。DRV8711DCPR的设计灵活性和应变能力使其成为许多设计师和工程师的首选。 芯片DRV8711DCPR的详细参数 DRV8711DCPR具有多种电气和机械特性,使其适合多种应用场景。以下是该芯片的一些主要参数: - 工作电压范围:8V至40V - 输出电流:可达2A - 输入电流:待机时小于1mA - 微步分辨率:可达1/128步 - 控制模式:支持PWM控制、DIR控制等多种模式 - 驱动方式:能够以高达85%效率的方式工作 - 过流保护:具有内置的过流保护功能,以提高可靠性 - 热保...

产品型号DRV8711DCPR的Datasheet PDF文件预览

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DRV8711  
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SLVSC40 JUNE 2013  
STEPPER MOTOR CONTROLLER IC  
1
FEATURES  
2
Pulse Width Modulation (PWM) Microstepping  
Motor Driver  
Protection and Diagnostic Features  
Overcurrent Protection (OCP)  
Built-In 1/256-Step Microstepping Indexer  
Drives External N-Channel MOSFETs  
Optional STEP/DIR Pins  
Overtemperature Shutdown (OTS)  
Undervoltage Lockout (UVLO)  
Individual Fault Condition Indication Bits  
Fault Condition Indication Pin  
Optional PWM Control Interface for DC  
Motors  
Flexible Decay Modes, Including Automatic  
Mixed Decay Mode  
APPLICATIONS  
Office Automation Machines  
Factory Automation  
Textile Machines  
Stall Detection With Optional BEMF Output  
Highly cConfigurable Va SPI Serial Interface  
Internal Reference and Torque DAC  
8-V to 52-V Operating Supply Voltage Range  
Scalable Output Current  
Robotics  
Thermally Enhanced Surface Mount Package  
5-V Regulator Capable of 10-mA Load  
DESCRIPTION  
The DRV8711 is a stepper motor controller that uses external N-channel MOSFETs to drive a bipolar stepper  
motor or two brushed DC motors. A microstepping indexer is integrated, which is capable of step modes from full  
step to 1/256-step.  
An ultra-smooth motion profile can be achieved using adaptive blanking time and various current decay modes,  
including an auto-mixed decay mode. Motor stall is reported with an optional back-EMF output.  
A simple step/direction or PWM interface allows easy interfacing to controller circuits. A SPI serial interface is  
used to program the device operation. Output current (torque), step mode, decay mode, and stall detection  
functions are all programmable via a SPI serial interface.  
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage  
lockout and overtemperature. Fault conditions are indicated via a FAULTn pin, and each fault condition is  
reported via a dedicated bit through SPI.  
The DRV8811 is packaged in a PowerPAD™ 38-pin HTSSOP package with thermal pad (Eco-friendly: RoHS  
and no Sb/Br).  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
Reel of 2000  
Tube of 40  
DRV8711DCPR  
–40°C to 85°C PowerPAD™ (HTSSOP) – PWP  
DRV8711  
DRV8711DCP  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
DRV8711  
SLVSC40 JUNE 2013  
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FUNCTIONAL BLOCK DIAGRAM  
VM  
0.1µF  
+
1µF  
100µF  
0.01µF  
VM  
CP2  
CP1  
VCP  
VM  
5V OUT  
VM  
VM  
A1HS  
Charge  
Pump  
HS Gate Drive  
V5  
Gate  
AOUT1  
Drive  
&
OCP  
0.1µF  
Regs  
VINT  
A1LS  
PWM  
logic  
1µF  
DCM  
VM  
A2HS  
Step  
Motor  
Gate  
Drive  
&
AOUT2  
Over-  
Temp  
SLEEPn  
RESET  
OCP  
A2LS  
+
-
UVLO  
PUC  
STEP/AIN1  
DIR/AIN2  
Comp  
Comp  
+
-
AISENP  
AISENN  
-
ISEN  
amp  
+
+
-
BIN1  
BIN2  
SIN  
VM  
X
B1HS  
DAC  
Gate  
Drive  
&
Torque  
DAC  
BOUT1  
OCP  
B1LS  
SCS  
Logic  
PWM  
logic  
DCM  
SCLK  
VM  
B2HS  
SDATI  
Gate  
Drive  
&
BOUT2  
Reference  
OCP  
B2LS  
SDATO  
+
-
Comp  
Comp  
+
-
BISENP  
BISENN  
-
FAULTn  
ISEN  
amp  
+
+
-
SIN  
X
STALLn / BEMFVn  
DAC  
Torque  
DAC  
Stall detect  
BEMF  
1nF  
GND  
2
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SLVSC40 JUNE 2013  
TERMINAL FUNCTIONS  
NAME  
NO.  
I/O(1)  
DESCRIPTION  
POWER AND GROUND  
All pins must be connected to ground  
EXTERNAL COMPONENTS OR CONNECTIONS  
GND  
5, 29,  
38,  
-
Device ground  
PPAD  
VM  
4
7
6
-
-
Bridge A power supply  
Internal logic supply voltage  
5-V regulator output  
Connect to motor supply voltage. Bypass to GND with a 0.01-μF  
ceramic capacitor plus a 100-μF electrolytic capacitor.  
VINT  
V5  
Logic supply voltage. Bypass to GND with a 1-μF 6.3-V X7R ceramic  
capacitor.  
O
5-V linear regulator output. Bypass to GND with a 0.1-μF 10-V X7R  
ceramic capacitor.  
CP1  
CP2  
VCP  
1
2
3
IO  
IO  
IO  
Charge pump flying capacitor  
Charge pump flying capacitor  
High-side gate drive voltage  
Connect a 0.1-μF X7R capacitor between CP1 and CP2. Voltage  
rating must be greater than applied VM voltage.  
Connect a 1-μF 16-V X7R ceramic capacitor to VM  
CONTROL  
SLEEPn  
8
I
I
Sleep mode input  
Logic high to enable device, logic low to enter low-power sleep mode  
STEP/AIN1  
10  
Step input/Bridge A IN1  
Indexer mode: Rising edge causes the indexer to move one step.  
External PWM mode: controls bridge A OUT1 Internal pulldown.  
DIR/AIN2  
BIN1  
11  
12  
13  
9
I
I
I
I
Direction input/Bridge A IN2  
Bridge B IN1  
Indexer mode: Level sets the direction of stepping.  
External PWM mode: controls bridge A OUT2 Internal pulldown.  
Indexer mode: No function  
External PWM mode: controls bridge B OUT1 Internal pulldown.  
BIN2  
Bridge B IN2  
Indexer mode: No function  
External PWM mode: controls bridge B OUT2 Internal pulldown.  
RESET  
Reset input  
Active-high reset input initializes all internal logic and disables the H-  
bridge outputs. Internal pulldown.  
SERIAL INTERFACE  
SCS  
16  
14  
I
I
Serial chip select input  
Serial clock input  
Active high to enable serial data transfer. Internal pulldown.  
SCLK  
Rising edge clocks data into part for write operations. Falling edge  
clocks data out of part for read operations. Internal pulldown.  
SDATI  
15  
17  
I
Serial data input  
Serial data output  
Serial data input from controller. Internal pulldown.  
SDATO  
O
Serial data output to controller. Open-drain output requires external  
pull-up.  
STATUS  
STALLn/  
BEMFVn  
19  
OD  
Stall/Back EMF valid  
Internal stall detect mode: logic low when motor stall detected.  
External stall detect mode: Active low when valid back EMF  
measurement is ready.  
Open-drain output requires external pullup.  
FAULTn  
BEMF  
18  
20  
OD  
O
Fault  
Logic low when in fault condition. Open-drain output requires external  
pullup.  
Faults: OCP, PDF, OTS, UVLO  
Back EMF  
Analog output voltage represents motor back EMF. Place a 1-nF low-  
leakage capacitor to ground on this pin.  
OUTPUTS  
A1HS  
36  
37  
35  
31  
30  
32  
34  
33  
27  
O
I
Bridge A out 1 HS gate  
Bridge A output 1  
Connect to gate of HS FET for bridge A out 1  
Connect to output node of external FETs of bridge A out 1  
Connect to gate of LS FET for bridge A out 1  
Connect to gate of HS FET for bridge A out 2  
Connect to output node of external FETs of bridge A out 2  
Connect to gate of LS FET for bridge A out 2  
Connect to current sense resistor for bridge A  
Connect to ground at current sense resistor for bridge A  
Connect to gate of HS FET for bridge B out 1  
AOUT1  
A1LS  
O
O
I
Bridge A out 1 LS gate  
Bridge A out 2 HS gate  
Bridge A output 2  
A2HS  
AOUT2  
A2LS  
O
I
Bridge A out 2 LS gate  
Bridge A Isense + in  
Bridge A Isense - in  
Bridge B out 1 HS gate  
AISENP  
AISENN  
B1HS  
I
O
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output  
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TERMINAL FUNCTIONS (continued)  
NAME  
BOUT1  
NO.  
I/O(1)  
DESCRIPTION  
Bridge B output 1  
EXTERNAL COMPONENTS OR CONNECTIONS  
28  
26  
22  
21  
23  
25  
24  
I
O
O
I
Connect to output node of external FETs of bridge B out 1  
Connect to gate of LS FET for bridge B out 1  
B1LS  
Bridge B out 1 LS gate  
Bridge B out 2 HS gate  
Bridge B output 2  
B2HS  
Connect to gate of HS FET for bridge B out 2  
BOUT2  
B2LS  
Connect to output node of external FETs of bridge B out 2  
Connect to gate of LS FET for bridge B out 2  
O
I
Bridge B out 2 LS gate  
Bridge B Isense + in  
Bridge B Isense - in  
BISENP  
BISENN  
Connect to current sense resistor for bridge B  
I
Connect to ground at current sense resistor for bridge B  
CRITICAL COMPONENTS  
PIN  
NAME  
VM  
COMPONENT  
4
3
100-µF electrolytic rated for VM voltage to GND 0.01-µF ceramic rated for VM voltage to GND  
1-µF ceramic X7R rated 16 V to VCP  
VCP  
1, 2  
6
CP1, CP2  
V5  
0.1-µF rated for VM + 12 V between these pins  
0.1-µF ceramic X7R rated 6.3 V to GND  
7
VINT  
1-µF ceramic X7R rated 6.3 V to GND  
17  
18  
19  
20  
SDATO  
FAULTn  
STALLn/BEMFVn  
BEMF  
Requires external pullup to logic supply  
Requires external pullup to logic supply  
Requires external pullup to logic supply  
1-nF low-leakage capacitor to GND  
DCP (HTSSOP) PACKAGE  
1
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
CP1  
CP2  
VCP  
VM  
GND  
GND  
2
AOUT1  
A1HS  
A1LS  
AISENP  
AISENN  
A2LS  
A2HS  
AOUT2  
GND  
BOUT1  
B1HS  
B1LS  
BISENP  
BISENN  
B2LS  
B2HS  
BOUT2  
BEMF  
3
4
5
6
V5  
VINT  
7
8
SLEEPn  
RESET  
STEP / AIN1  
DIR / AIN2  
BIN1  
9
GND  
(PPAD)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
BIN2  
SCLK  
SDATI  
SCS  
SDATO  
FAULTn  
STALLn / BEMFVn  
4
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SLVSC40 JUNE 2013  
ABSOLUTE MAXIMUM RATINGS(1) (2) (3)  
over operating free-air temperature range (unless otherwise noted)  
DRV8711  
UNIT  
Power supply voltage range  
-0.6 to 60  
-0.6 to VM + 12  
-0.6 to 5.5  
V
V
V
V
Charge pump voltage range (CP1, CP2, VCP)  
5V regulator voltage (V5)  
Internal regulator voltage (VINT)  
-0.6 to 2.0  
Digital pin voltage range (SLEEPn, RESET, STEP/AIN1, DIR/AIN2, BIN1, BIN2, SCS, SCLK, SDATI,  
SDATO, FAULTn, STALLn/BEMFVn)  
-0.6 to 5.5  
V
High-side gate drive pin voltage range (A1HS, A2HS, B1HS, B2HS)  
Low-side gate drive pin voltage range (A1LS, A2LS, B1LS, B2LS)  
Phase node pin voltage range (AOUT1, AOUT2, BOUT1, BOUT2)  
ISENSEx pin voltage (AISENP, AISENN, BISENP, BISENN)  
BEMF pin voltage range (BEMF)  
-0.6 to VM + 12  
-0.6 to 12  
V
V
-0.6 to VM  
-0.7 to +0.7  
-0.6 to VM  
-40 to 150  
-60 to 150  
V
V
V
Operating virtual junction temperature range, TJ  
°C  
°C  
Storage temperature range, Tstg  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to network ground terminal.  
(3) Power dissipation and thermal limits must be observed.  
THERMAL INFORMATION  
DRV8711  
THERMAL METRIC(1)  
DCP  
38 PINS  
32.7  
UNITS  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
θJCtop  
θJB  
17.2  
14.3  
°C/W  
ψJT  
0.5  
ψJB  
14.1  
θJCbot  
0.9  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-  
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
Spacer  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
8
NOM  
MAX  
52  
UNIT  
V
VM  
IVS  
TA  
Motor power supply voltage range  
V5 external load current  
0
10  
mA  
°C  
Operating ambient temperature range  
-40  
85  
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MAX UNIT  
ELECTRICAL CHARACTERISTICS  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
Power Supplies  
IVM  
VM operating supply current  
VM sleep mode supply current  
VM = 24 V  
17  
65  
20  
98  
8
mA  
IVMQ  
VM = 24 V, SLEEPn = 0  
VM rising  
μA  
7.1  
6.3  
VUVLO  
VM undervoltage lockout voltage  
V
VM falling  
Internal Linear Regulators  
V5  
V5 output voltage  
VINT voltage  
V
M 12 V, IOUT = 1 mA - 10 mA  
4.8  
1.7  
5
5.2  
1.9  
V
V
VINT  
No external load – reference only  
1.8  
Logic-Level Inputs  
VIL  
VIH  
VHYS  
IIL  
Input low voltage  
0.8  
V
V
Input high voltage  
Input hysteresis voltage  
Input low current  
1.5  
300  
50  
mV  
μA  
μA  
VIN = 0 V  
VIN = 5 V  
-5  
5
IIH  
Input high current  
30  
70  
SDATAO, STALLn, FAULTn OUTPUTS (Open-Drain Outputs)  
VOL  
IOH  
Output low voltage  
IO = 5 mA  
VO = 3.3 V  
0.5  
1
V
Output high leakage current  
µA  
MOSFET Drivers  
VOUTH High-side gate drive output voltage  
VOUTL  
VM = 24 V, IO = 100 μA  
VM = 24 V, IO = 100 μA  
DTIME = 00  
VM+10  
10  
V
V
Low-side gate drive output voltage  
400  
450  
650  
850  
50  
DTIME = 01  
Output dead time digital delay (dead  
time is enforced in analog circuits)  
tDEAD  
IOUTH  
IOUTl  
ns  
mA  
mA  
ns  
DTIME = 10  
DTIME = 11  
IDRIVEP = 00  
IDRIVEP = 01  
IDRIVEP = 10  
IDRIVEP = 11  
IDRIVEN = 00  
IDRIVEN = 01  
IDRIVEN = 10  
IDRIVEN = 11  
TDRIVEP = 00  
TDRIVEP = 01  
TDRIVEP = 10  
TDRIVEP = 11  
TDRIVEN = 00  
TDRIVEN = 01  
TDRIVEN = 10  
TDRIVEN = 11  
100  
150  
200  
100  
150  
200  
400  
250  
500  
1000  
2000  
250  
500  
1000  
2000  
Peak output current gate drive  
(source)  
Peak output current gate drive (sink)  
Peak current drive time (source)  
Peak current drive time (sink)  
tDRIVE  
tDRIVE  
ns  
Motor Driver  
tOFF  
PWM off time adjustment range  
Set by TOFF register  
0.5  
0.5  
128  
μs  
μs  
tBLANK  
Current sense blanking time  
Set by TBLANK register  
5.12  
6
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ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
Protection Circuits  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
OCPTH = 00  
OCPTH = 01  
OCPTH = 10  
OCPTH = 11  
Die temperature  
160  
380  
620  
840  
150  
250  
500  
750  
1000  
160  
20  
320  
580  
mV  
850  
Overcurrent protection trip level  
(Voltage drop across external FET)  
VOCP  
1200  
tTSD  
tHYS  
Thermal shutdown temperature(1)  
Thermal shutdown hysteresis  
180  
°C  
°C  
Current Sense Amplifiers  
ISGAIN = 00  
5
10  
ISGAIN = 01  
AV  
Gain  
V/V  
ns  
ISGAIN = 10  
20  
ISGAIN = 11  
40  
ISGAIN = 00, ΔVIN = 400 mV  
ISGAIN = 01, ΔVIN = 200 mV  
ISGAIN = 10, ΔVIN = 100 mV  
ISGAIN = 11, ΔVIN = 50 mV  
ISGAIN = 00, input shorted  
150  
300  
600  
1.2  
tSET  
Settling time (to ±1%)  
µs  
VOFS  
VIN  
Offset voltage  
4
mV  
mV  
Input differential voltage range  
-300  
2.50  
300  
Current Control DACs  
Resolution  
256  
steps  
µs  
Full-scale step response  
Full-scale (reference) voltage  
(1) Not tested in production - guaranteed by design.  
10% to 90%  
5
3
VREF  
2.75  
V
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SPI INTERFACE TIMING REQUIREMENTS  
over operating free-air temperature range (unless otherwise noted)  
No.  
1
PARAMETER  
CONDITIONS  
MIN  
250  
25  
25  
5
MAX UNIT  
tCYC  
Clock cycle time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
tCLKH  
Clock high time  
3
tCLKL  
Clock low time  
4
tSU(SDATI)  
tH(SDATI)  
tSU(SCS)  
tH(SCS)  
tL(SCS)  
Setup time, SDATI to SCLK  
Hold time, SDATI to SCLK  
Setup time, SCS to SCLK  
Hold time, SCS to SCLK  
5
1
6
5
7
1
8
Inactive time, SCS (between writes)  
100  
9
tD(SDATO)  
tSLEEP  
Delay time, SCLK to SDATO (during read)  
10  
1
ns  
ms  
μs  
Wake time (SLEEPn inactive to high-side gate drive enabled)  
Delay from power-up or RESETn high until serial interface functional  
tRESET  
10  
7
6
8
SCS  
1
SCLK  
SDATI  
2
3
X
X
4
5
9
SDATO  
valid  
SDATO  
8
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INDEXER TIMING REQUIREMENTS  
over operating free-air temperature range (unless otherwise noted)  
No.  
1
PARAMETER  
fSTEP  
CONDITIONS  
MIN  
MAX UNIT  
Step frequency  
250 kHz  
2
tWH(STEP)  
tWL(STEP)  
tSU(STEP)  
tH(STEP)  
Pulse duration, STEP high  
Pulse duration, STEP low  
1.9  
1.9  
μs  
μs  
ns  
ns  
3
4
Setup time, command to STEP rising  
Hold time, command to STEP rising  
200  
200  
5
1
3
2
STEP  
DIR, MODE  
5
4
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FUNCTIONAL DESCRIPTION  
PWM Motor Drivers  
The DRV8711 contains two H-bridge motor pre-drivers with current-control PWM circuitry.  
More detailed descriptions of the sub-blocks are described in the following sections.  
Direct PWM Input Mode  
Direct PWM mode is selected by setting the PWMMODE bit in the OFF register. In direct PWM input mode, the  
AIN1, AIN2, BIN1, and BIN2 directly control the state of the output drivers. This allows for driving up to two  
brushed DC motors. The logic is shown below:  
Table 1. Direct PWM Input Mode Logic  
xIN1  
xIN2  
xOUT1  
xOUT2  
OPERATION  
Asynchronous Fast Decay  
Reverse Drive  
0
0
1
1
0
1
0
1
Z
L
Z
H
L
H
L
Forward Drive  
L
Slow Decay  
Note that if mixed or auto mixed decay modes are used, they will apply to every cycle, since current change  
information is not available.  
In direct PWM mode, the current control circuitry is still active. The full-scale VREF is set to 2.75 V. The  
TORQUE register may be used to scale this value, and the ISEN sense amp gain may still be set using the  
ISGAIN bits of the CTRL register.  
VM  
x1HS  
Gate  
Drive  
xOUT1  
xIN1  
xIN2  
&
OCP  
x1LS  
PWM  
logic  
VM  
x2HS  
Gate  
Drive  
&
xOUT2  
OCP  
x2LS  
+
-
RISENSE  
Comp  
Comp  
+
-
xISENP  
xISENN  
-
ISEN  
amp  
+
+
-
VREF  
ISGAIN  
X
1 V  
Torque  
DAC  
TORQUE  
Figure 1. Direct PWM Input Mode  
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The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation  
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage  
and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current  
chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between  
500 nS and 128 µS by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is re-  
enabled, starting another PWM cycle.  
The chopping current is set by a comparator which compares the voltage across a current sense resistor  
connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The  
current sense amplifier is programmable in the CTRL register.  
When driving in PWM mode, the chopping current is calculated as follows:  
2.75V · TORQUE  
ICHOP =  
256 ·ISGAIN·RISENSE  
(1)  
Where TORQUE is the setting of the TORQUE bits, and ISGAIN is the programmed gain of the ISENSE  
amplifiers (5, 10, 20, or 40).  
Microstepping Indexer  
Built-in indexer logic in the DRV8711 allows a number of different stepping configurations. The MODE bits in the  
CTRL register are used to configure the stepping format as shown in the table below:  
Table 2. Microstepping Indexer Logic  
MODE3  
MODE2  
MODE1  
MODE0  
STEP MODE  
Full step (2-phase excitation)  
with 71% current  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1/2 step  
1/4 step  
1/8 step  
1/16 step  
1/32 step  
1/64 step  
1/128 step  
1/256 step  
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Table 3 shows the relative current and step directions for full-step through 1/8-step operation. Higher  
microstepping resolutions follow the same pattern. The AOUT current is the sine of the electrical angle; BOUT  
current is the cosine of the electrical angle.  
The reset state is 45°. This state is entered at power-up or application of RESETn. This is shown in the table  
below by cells shaded in yellow.  
Table 3. Step Directions  
ELECTRICAL  
ANGLE  
(DEGREES)  
AOUT CURRENT BOUT CURRENT  
(% FULL-SCALE) (% FULL-SCALE)  
FULL STEP  
1/2 STEP  
1/4 STEP  
1/8 STEP  
1
1
1
0
20  
100  
98  
0
11.325  
22.5  
2
2
3
3
38  
92  
4
56  
83  
33.75  
45 (home state)  
56.25  
67.5  
1
2
3
4
5
6
7
8
5
71  
71  
6
83  
56  
4
7
92  
38  
8
98  
20  
78.75  
90  
5
9
100  
98  
0
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
-20  
-38  
-56  
-71  
-83  
-92  
-98  
-100  
-98  
-92  
-83  
-71  
-56  
-38  
-20  
0
101.25  
112.5  
123.75  
135  
6
92  
83  
2
3
4
7
71  
56  
146.25  
157.5  
168.75  
180  
8
38  
20  
9
0
-20  
-38  
-56  
-71  
-83  
-92  
-98  
-100  
-98  
-92  
-83  
-71  
-56  
-38  
-20  
191.25  
202.5  
213.75  
225  
10  
11  
12  
13  
14  
15  
16  
236.25  
247.5  
258.75  
270  
20  
281.25  
292.5  
303.75  
315  
38  
56  
71  
83  
326.25  
337.5  
348.75  
92  
98  
At each rising edge of the STEP input, or each time a '1' is written to the RSTEP bit in the CTRL register, the  
indexer travels to the next state in the table. The direction is shown with the DIR pin high and the RDIR bit in the  
CTRL register set to '0', or the DIR pin low and the RDIR bit set to '1'. If the DIR pin is low with the RDIR bit '0',  
or the DIR pin is high with the RDIR bit '1', the sequence is reversed. Positive current is defined as xOUT1 =  
positive with respect to xOUT2.  
Note that if the step mode is changed while stepping, the indexer will advance to the next valid state for the new  
MODE setting at the rising edge of STEP.  
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Current Regulation  
The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation  
circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage  
and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current  
chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between  
500 nS and 128 µS by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is re-  
enabled, starting another PWM cycle.  
In stepping motors, current regulation is used to vary the current in the two windings in a sinusoidal fashion to  
provide smooth motion.  
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor  
connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The  
current sense amplifier is programmable in the CTRL register.  
VM  
x1HS  
Gate  
Drive  
xOUT1  
&
OCP  
Registers  
x1LS  
PWM  
logic  
VM  
x2HS  
Gate  
Drive  
&
xOUT2  
OCP  
x2LS  
+
-
RISENSE  
Comp  
Comp  
+
-
xISENP  
xISENN  
-
+
ISEN  
amp  
+
-
2.75 V  
SIN  
DAC  
Indexer  
ISGAIN  
X
1 V  
Torque  
DAC  
TORQUE  
Figure 2. PWM Chopping Current  
To generate the reference voltage for the current chopping comparator, the output of a sine lookup table is  
multiplied by the value of the bits in the TORQUE register. This result is applied to a sine-weighted DAC, whose  
full-scale output voltage is 2.75 V.  
Therefore, the full-scale (100%) chopping current is calculated as follows:  
2.75V · TORQUE  
IFS =  
256 ·ISGAIN·RISENSE  
(2)  
Where TORQUE is the setting of the TORQUE bits, and ISGAIN is the programmed gain of the ISENSE  
amplifiers (5, 10, 20, or 40).  
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Example:  
If a 0.1-Ω sense resistor is used, ISGAIN is set to 0 (gain of 5), and TORQUE is set to 255, the full-scale (100%)  
chopping current will be (2.75V * 255) / (256 * 5 * 0.1Ω) = 5.5A.  
Decay Modes  
During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current  
chopping threshold is reached. This is shown in Figure 3, Item 1. The current flow direction shown indicates  
positive current flow in the step table below.  
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or  
slow decay.  
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to  
allow winding current to flow in a reverse direction. If synchronous rectification is enabled (SRn pin logic low), the  
opposite FETs are turned on; as the winding current approaches zero, the bridge is disabled to prevent any  
reverse current flow. If SRn is high, current is recirculated through the body diodes, or through external Schottky  
diodes. Fast-decay mode is shown in Figure 3, Item 2.  
In slow-decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is  
shown in Figure 3, Item 3.  
VM  
PWM  
ON  
PWM OFF  
Slow Decay  
Fast Decay  
1
2
3
Drive Current  
1
Fast decay (reverse)  
Slow decay (brake)  
xOUT2  
xOUT1  
3
2
Mixed Decay  
TDECAY  
TBLANK  
TOFF  
Itrip  
Figure 3. Decay Modes  
The DRV8711 supports fast decay and slow decay modes in both indexer and direct PWM modes. In addition, in  
indexer mode only, it supports fixed mixed decay and auto mixed decay modes. Decay mode is selected by the  
DECMOD bits in the DECAY register.  
Mixed decay mode begins as fast decay, but after a programmable period of time (set by the TDECAY bits in the  
DECAY register) switches to slow decay mode for the remainder of the fixed off time. Even if mixed decay is  
selected, if the current is increasing or remaining the same (per the step table), then slow decay is used.  
Auto mixed decay mode samples the current level at the end of the blanking time, and if the current is above the  
Itrip threshold, immediately changes the H-bridge to fast decay. During fast decay, the (negative) current is  
monitored, and when it falls below the Itrip threshold (and another blanking time has passed), the bridge is  
switched to slow decay. Once the fixed off time expires, a new cycle is started.  
If the bridge is turned on and at the end of TBLANK the current is below the Itrip threshold, the bridge remains on  
until the current reaches Itrip. Then slow decay is entered for the fixed off time, and a new cycle begins.  
Refer to Figure 4 and Figure 5.  
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The upper waveform shows the behavior if I < Itrip at the end of tBLANK. Note that (at slow motor speeds, where  
back EMF is not significant), the current increase during the ON phase is the same magnitude as the current  
decrease in fast decay, since both times are controlled by tBLANK, and the rate of change is the same (full VM is  
applied to the load inductance in both cases, but in opposite directions). In this case, the current will gradually be  
driven down until the peak current is just hitting Itrip at the end of the blanking time, after which some cycles will  
be slow decay, and some will be mixed decay.  
tON  
tON  
tOFF  
tOFF  
tBLANK  
tBLANK  
I below Itrip  
after tBLANK  
Itrip  
At Itrip and after  
tBLANK, slow decay  
I < Itrip  
tON  
tON  
tOFF  
tOFF  
On  
tBLANK  
tBLANK tBLANK  
tBLANK  
I above Itrip  
after tBLANK  
Fast  
Decay  
Itrip  
Slow  
Decay  
I > Itrip, start  
fast decay  
When I < Itrip in fast decay  
and tBLANK expires, change  
to slow decay  
Figure 4. I < Itrip at the End of tBLANK  
If the Itrip level changes during a PWM cycle (in response to a step command to the indexer), the current cycle is  
immediately terminated, and a new cycle is begun. Refer to the drawing below.  
If the Itrip level has increased, the H-bridge will immediately turn on; if the Itrip level has decreased, fast decay  
mode is begun immediately. The top waveform shows what happens when the Itrip threshold decreases during a  
PWM cycle. The lower Itrip level results in the current being above the Itrip threshold at the end of tBLANK on  
the following cycle. Fast decay is entered until the current is driven below the Itrip threshold.  
tON  
tBLANK  
tON  
tBLANK  
tOFF  
tOFF  
Itrip decrease  
Itrip  
Decrease in Itrip terminates  
cycle, fast decay begins  
When I < Itrip in fast decay  
change to slow decay  
tON  
On  
tON  
tBLANK  
tBLANK  
tOFF  
Itrip increase  
Fast  
Decay  
Slow  
Decay  
Itrip  
Increase in Itrip terminates  
cycle, bridge turns on  
Figure 5. Itrip Level Changing During a PWM Cycle  
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Blanking Time  
After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before  
enabling the current sense circuitry. This blanking time is adjustable from 1 µS to 5.12 µs, in 20 ns increments,  
by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum on time of  
the PWM.  
The same blanking time is applied to the fast decay period in auto decay mode. The PWM will ignore any  
transitions on Itrip after entering fast decay mode, until the blanking time has expired.  
To provide better current control at very low current steps, an adaptive blanking time mode can be enabled by  
setting the ABT bit in the BLANK register. If ABT is set, at current levels below 30% of full scale current (as  
determined by the step table), the blanking time (so also the minimum on time) is cut in half, to 50% of the value  
programmed by the TBLANK bits.  
For higher degrees of micro-stepping it is recommended to enable ABT bit for better current regulation.  
Pre-Drivers  
An internal charge pump circuit and pre-drivers inside the DRV8711 directly drive N-channel MOSFETs, which  
drive the motor current.  
The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source  
currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2x the peak  
source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input  
capacitance and gate charge.  
When changing the state of the output, the peak current is applied for a short period of time (tDRIVE), to charge  
the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When  
selecting the gate drive strength for a given external FET, the selected current must be high enough to fully  
charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated  
in the FET.  
During high-side turn-on, the low-side gate is pulled low. This prevents the gate-source capacitance of the low-  
side FET from inducing turn-on.  
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and  
low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay  
can be selected by setting the DTIME bits in the CTRL register.  
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tDRIVE  
High Z  
High Z  
High Z  
Low Z  
HS drive  
(mA)  
Low  
Z
xHS  
(V)  
tDRIVE  
High Z  
Low Z  
High Z  
High Z  
LS drive  
(mA)  
Low  
Z
xLS  
(V)  
tDEAD  
tDEAD  
Figure 6. Pre-Drivers  
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Gate Pre-drive Source Capability  
I (mA) source  
I (mA) source  
200 mA  
TDRIVEP = 00  
TDRIVEP = 01  
200 mA  
150 mA  
100 mA  
50 mA  
IDRIVEP = 11  
IDRIVEP = 11  
150 mA  
100 mA  
IDRIVEP = 10  
IDRIVEP = 10  
IDRIVEP = 01  
IDRIVEP = 00  
IDRIVEP = 01  
IDRIVEP = 00  
50 mA  
Holding Current  
Holding Current  
t (ns)  
t (ns)  
250 ns 500 ns  
I (mA) source  
1 µs  
2 µs  
250 ns 500 ns  
I (mA) source  
1 µs  
2 µs  
TDRIVEP = 10  
TDRIVEP = 11  
200 mA  
150 mA  
100 mA  
200 mA  
IDRIVEP = 11  
IDRIVEP = 11  
IDRIVEP = 10  
150 mA  
100 mA  
IDRIVEP = 10  
IDRIVEP = 01  
IDRIVEP = 00  
IDRIVEP = 01  
IDRIVEP = 00  
50 mA  
50 mA  
Holding Current  
Holding Current  
t (ns)  
t (ns)  
250 ns 500 ns  
1 µs  
2 µs  
250 ns 500 ns  
1 µs  
2 µs  
Gate Pre-drive Sink Capability  
TDRIVEN = 00  
TDRIVEN = 01  
250 ns 500 ns  
1 µs  
2 µs  
250 ns 500 ns  
1 µs  
2 µs  
t (ns)  
t (ns)  
Holding Current  
Holding Current  
IDRIVEN = 00  
IDRIVEN = 00  
100 mA  
100 mA  
IDRIVEN = 01  
IDRIVEN = 10  
IDRIVEN = 11  
IDRIVEN = 01  
IDRIVEN = 10  
IDRIVEN = 11  
200 mA  
300 mA  
400 mA  
200 mA  
300 mA  
400 mA  
I (mA) sink  
250 ns 500 ns  
I (mA) sink  
250 ns 500 ns  
TDRIVEN = 10  
TDRIVEN = 11  
1 µs  
1 µs  
2 µs  
2 µs  
t (ns)  
t (ns)  
Holding Current  
Holding Current  
IDRIVEN = 00  
IDRIVEN = 00  
IDRIVEN = 01  
100 mA  
100 mA  
IDRIVEN = 01  
IDRIVEN = 10  
IDRIVEN = 11  
200 mA  
300 mA  
400 mA  
200 mA  
300 mA  
400 mA  
IDRIVEN = 10  
IDRIVEN = 11  
I (mA) sink  
I (mA) sink  
Figure 7. Gate Pre-Drive Source/Sink Capability  
Configuring Pre-drivers  
IDRIVE and TDRIVE are selected based on the size of external FETs used. These registers need to be  
configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and TDRIVE are chosen to  
be too low for a given FET, then the FET may not turn on completely. It is suggested to adjust these values in-  
system with the required external FETs and stepper motor in order to determine the best possible setting for any  
application.  
Note that TDRIVE will not increase the PWM time or change the PWM chopping frequency.  
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In a system with capacitor charge Q and desired rise time RT, IDRIVE and TDRIVE can be initially selected  
based on:  
IDRIVE > Q / RT  
TDRIVE > 2 x RT  
For best results, select the smallest IDRIVE and TDRIVE that meet the above conditions.  
Example:  
If the gate charge is 15 nC and the desired rise time is 400 ns, then select:  
IDRIVEP = 50 mA, IDRIVEN = 100 mA  
TDRIVEP = TDRIVEN = 1 µs  
External FET Selection  
In a typical setup, the DRV8711 can support external FETs over 50 nC each. However, this capacity can be  
lower or higher based on the device operation. For an accurate calculation of FET driving capacity, use the  
following equation.  
20mA ·(2 ·DTIME + TBLANK + TOFF)  
Q <  
4
(3)  
Example:  
If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0 (500 ns), then the DRV8711 will  
support Q < 11.5 nC FETs (please note that this is an absolute worst-case scenario with a PWM frequency  
~ 430 kHz).  
If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x14 (10 µs), then the DRV8711  
will support Q < 59 nC FETs (PWM frequency ~ 85 kHz).  
If a DTIME is set to 0 (400 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x60 (48 µs), then the DRV8711  
will support Q < 249 nC FETs (PWM frequency ~ 20 kHz).  
Stall Detection  
The DRV8711 implements a back EMF monitoring scheme that is capable of detecting a stall during stepper  
motor motion. This stall detection is intended to be used to get an indication when a motor is run into a  
mechanical stop, or when an increased torque load on the motor causes it to stall.  
To determine that a stall has occurred, a drop in motor back EMF is detected. The DRV8711 supports two  
methods of this detection: an automatic internal stall detection circuit, or the ability to use an external  
microcontroller to monitor back EMF.  
During a zero-current step, one side of the H-bridge is placed in a high impedance state, and the opposite low-  
side FET is turned on for a brief duration defined by TORQUE register SMPLTH bit [10:8]. This allows the current  
to decay quickly through the low-side FET and the opposite body diode. Which side of the bridge is tri-state and  
which one is driven low depends on the current direction on the previous step. The bridge with the high side that  
has been actively PWMed (at the beginning of the PWM cycle during blank time) prior to entering the zero-  
current step will be held low and the opposite side will be tri-stated.  
Back EMF is sampled on the tri-stated output pin at the end of SMPLTH time (TORQUE register bit [10:8]). The  
back EMF from the selected pin is divided by 4, 8, 16, or 32, depending on the setting of the VDIV bits in the  
STALL register. The voltage is buffered and held on an external capacitor placed on the BEMF pin. The signal on  
the BEMF output pin can be further processed by a microcontroller to implement more advanced control and stall  
detection algorithms.  
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VM  
AOUT1  
BEMF  
buffer  
2
VDIV  
VM  
Step  
Motor  
AOUT2  
2
control  
logic  
VDIV  
VM  
SDCNT  
To  
STATUS  
register  
2
STALLn/  
BEMFVn  
BOUT1  
+
-
comp  
counter  
2
VM  
VDIV  
reference  
1.80 V  
BOUT2  
8
DAC  
SDTHR  
SDTHR  
DAC  
2
VDIV  
Figure 8. Stall Detection  
Internal Stall Detection  
To use internal stall detection, the EXSTALL bit in the CTRL register is set to ‘0’. In this mode, the  
STALLn/BEMFVn output pin is used to signal a valid stall condition.  
Step time, or rate at which step input is applied to DRV8711, has to be greater than SMPLTH time for back EMF  
sampling.  
Using internal stall detection, a stall is detected when the sampled back EMF drops below the value set by the  
SDTHR bits in the STALL register. A programmable counter circuit allows the assertion of the STALLn output to  
be delayed until the back EMF has been sampled below the SDTHR value for more than one zero-current step.  
The counter is programmed by the SDCNT bits in the STALL register, and provides selections of 1, 2, 4, or 8  
steps.  
When the stall is detected (at the end of a SMPLTH interval), the STALLn/BEMFVn pin is driven active low, and  
the STD bit and the STDLAT bit in the STATUS register are set. The STALLn/BEMFVn pin will deassert and the  
STD bit will automatically clear at the next zero-current step if a stall condition is not detected, while the STDLAT  
bit will remain set until a '0' is written to it. The STDLAT is reset when the STD bit clears after the first zero-cross  
step that does not detect a stall condition.  
This stall detection scheme is only effective when the motor is stalled while running at or above some minimum  
speed. Since it relies on detecting a drop in motor back EMF, the motor must be rotating with sufficient speed to  
generate a detectable back EMF. During motor start-up, and at very slow step rates, the stall detection is not  
reliable.  
Since back EMF can only be sampled during a zero-current state, stall detection is not possible in full step mode.  
During full-step operation, the stall detect circuit is gated off to prevent false signaling of a stall.  
The correct setting of the SDTHR bits needs to be determined experimentally. It is dependent on many factors,  
including the electrical and mechanical characteristics of the load, the peak current setting, and the supply  
voltage.  
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External Stall Detection  
To use an external microcontroller to manage stall detection, the EXSTALL bit in the CTRL register is set to ‘1’.  
In this mode, the STALLn / BEMFVn output pin is used to signal a valid back EMF measurement is ready. In  
addition, the SDT and SDTLAT bits are also set at this time.  
BEMFVn and BEMF are still valid outputs in this mode even if the step time is smaller than SMPLTH time.  
When the BEMFVn pin goes active low, it is an indication that a valid back EMF voltage measurement is  
available. This signal could be used, for example, to trigger an interrupt on a microcontroller. The microcontroller  
can then sample the voltage present (using an A/D converter) on the BEMF pin.  
After sampling the back EMF voltage, the microcontroller writes a ‘0’ to the SDTLAT bit to clear the SDT bit and  
BEMFVn pin, in preparation for the next back EMF sample. If the SDTLAT bit is not cleared by the  
microcontroller, it will automatically be cleared in the next zero-current step.  
For either internal or external stall detection, at very high motor speeds when the PWM duty cycle approaches  
100%, the inductance of the motor and the short duration of each step may cause the time required for current  
recirculation to exceed the step time. In this case, back EMF will not be correctly sampled, and stall detection  
cannot function. This condition occurs most at high degrees of micro-stepping, since the zero current step lasts  
for a shorter duration. It is advisable to run the motor at lower degrees of micro-stepping at higher speeds to  
allow time for current recirculation if stall detection is needed in this condition.  
RESET and SLEEPn Operation  
An internal power-up reset circuit monitors the voltage applied to the VM pin. If VM falls below the VM  
undervoltage lockout voltage, the part is reset, as described below for the case of asserting the RESET pin.  
If the RESET pin is asserted, all internal logic including the indexer is reset. All registers are returned to their  
initial default conditions. The power stage will be disabled, and all inputs, including STEP and the serial interface,  
are ignored when RESET is active.  
On exiting reset state, some time (approximately 1 mS) needs to pass before the part is fully functional.  
Applying an active low input to the SLEEPn input pin will place the device into a low power state. In sleep mode,  
the motor driver circuitry is disabled, the gate drive regulator and charge pump are disabled, and all analog  
circuitry is placed into a low power state. The digital circuitry in the device still operates, so the device registers  
can still be accessed via the serial interface.  
When SLEEPn is active, the RESET pin does not function. SLEEPn must be exited before RESET will take  
effect.  
When exiting from sleep mode, some time (approximately 1 mS) needs to pass before applying a STEP input, to  
allow the internal circuitry to stabilize.  
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Microstepping Drive Current  
The following plots are examples of stepper motor current in one of the windings. Since these waveforms are  
dependent on DRV8711 register settings as well as the external FETs, sense resistor, and stepper motor, they  
should only be used as a reference.  
1/4 stepping  
1/8 stepping  
Current  
Current  
STEP  
STEP  
1/16 stepping  
1/128 stepping  
Current  
Current  
STEP  
STEP  
Figure 9. Microstepping Drive Current  
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Protection Circuits  
The DRV8711 is fully protected against undervoltage, overcurrent and overtemperature events.  
Overcurrent Protection (OCP)  
Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven  
FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period  
specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. When operating in direct  
PWM mode, during an OCP event, the H-bridge experiencing the OCP event is disabled; if operating in indexer  
mode, both H-bridges will be disabled. In addition, the corresponding xOCP bit in the STATUS register is set,  
and the FAULTn pin is driven low. The H-bridge(s) will remain off, and the xOCP bit will remain set, until it is  
written to 0, or the device is reset.  
Pre-Driver Fault  
If excessive current is detected on the gate drive outputs (which would be indicative of a failed/shorted output  
FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the STATUS register is set,  
and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will remain set until it is written  
to 0, or the device is reset.  
Thermal Shutdown (TSD)  
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS  
register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level  
operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation  
has resumed.  
Undervoltage Lockout (UVLO)  
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-  
bridge will be disabled, the UVLO bit in the STATUS register will be set, and the FAULTn pin will be driven low.  
Operation will resume and the UVLO bit will reset when VM rises above the UVLO threshold. The FAULTn pin  
will be released after operat ion has resumed.  
During any of these fault conditions, the STEP input pin will be ignored.  
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Serial Data Format  
The serial data consists of a 16-bit serial write, with a read/write bit, 3 address bits and 12 data bits. The three  
address bits identify one of the registers defined in the register section above.  
To write to a register, data is shifted in after the address as shown in the timing diagram below:  
SCS  
Note 1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
SCLK  
SDATI  
WRT  
A2  
A1  
A0  
D11  
D10  
D9  
D8  
X
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
A. Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used.  
Figure 10. Write Operation  
Data may be read from the registers through the SDATO pin. During a read operation, only the address is used  
form the SDATI pin; the data bits following are ignored. Reading is enabled by setting the READ bit at the  
beginning of the access:  
SCS  
Note 1  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
SCLK  
SDATI  
READ  
A2  
A1  
A0  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SDATO  
(1) Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used.  
Figure 11. Read Operation  
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CONTROL REGISTERS  
The DRV8711 uses internal registers to control the operation of the motor. The registers are programmed via a  
serial SPI communications interface. At power-up or reset, the registers will be pre-loaded with default values as  
shown below.  
Following is a map of the DRV8711 registers:  
DRV8711 REGISTER MAP  
Address  
Name  
CTRL  
11  
10  
9
8
7
6
5
4
3
2
1
0
Hex  
ENBL  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
00  
DTIME  
ISGAIN  
EXSTALL  
MODE  
RSTEP  
RDIR  
TORQUE  
OFF  
Reserved  
01  
02  
03  
04  
05  
06  
07  
SMPLTH  
TORQUE  
TOFF  
Reserved  
Reserved  
PWMMODE  
ABT  
BLANK  
DECAY  
STALL  
DRIVE  
STATUS  
Name  
TBLANK  
TDECAY  
SDTHR  
Reserved  
DECMOD  
VDIV  
SDCNT  
IDRIVEP  
IDRIVEN  
TDRIVEP  
TDRIVEN  
OCPDEG  
OCPTH  
Reserved  
STD  
6
UVLO  
5
APDF  
3
BOCP  
2
AOCP  
1
OTS  
0
STDLAT  
7
BPDF  
4
Address  
Hex  
11  
10  
9
8
Figure 12. DRV8711 Register Map  
Individual register contents are defined below.  
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CTRL Register  
Address = 0x00h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
0: Disable motor  
1: Enable motor  
0
ENBL  
1
R/W  
0
0: Direction set by DIR pin  
1: Direction set by inverse of DIR pin  
1
2
RDIR  
1
1
R/W  
W
0
0
0: No action  
RSTEP  
1: Indexer will advance one step; automatically cleared after write  
0000: Full-step, 71% current  
0001: Half step  
0010: 1/4 step  
0011: 1/8 step  
0100: 1/16 step  
0101: 1/32 step  
6-3  
MODE  
4
R/W  
110  
0110: 1/64 step  
0111: 1/128 step  
1000: 1/256 step  
1001 – 1111: Reserved  
0: Internal stall detect  
1: External stall detect  
7
EXSTALL  
ISGAIN  
1
2
R/W  
R/W  
0
0
ISENSE amplifier gain set  
00: Gain of 5  
01: Gain of 10  
9-8  
10: Gain of 20  
11: Gain of 40  
Dead time set  
00: 400 ns dead time  
01: 450 ns dead time  
10: 650 ns dead time  
11: 850 ns dead time  
11-10  
DTIME  
2
R/W  
11  
TORQUE Register  
Address = 0x01h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
7-0  
TORQUE  
8
R/W  
0xFFh  
Sets full-scale output current for both H-bridges  
Back EMF sample threshold  
000: 50 µs  
001: 100 µs  
010: 200 µs  
10-8  
11  
SIMPLTH  
Reserved  
3
1
R/W  
1
-
011: 300 µs  
100: 400 µs  
101: 600 µs  
110: 800 µs  
111: 1000 µs  
-
Reserved  
OFF Register  
Address = 0x02h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
Sets fixed off time, in increments of 500 ns  
0x00h: 500 ns  
7-0  
TOFF  
8
R/W  
0x30h  
0xFFh: 128 µs  
0: Use internal indexer  
1: Bypass indexer, use xINx inputs to control outputs  
8
PWMMODE  
Reserved  
1
3
R/W  
-
0
-
11-9  
Reserved  
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BLANK Register  
Address = 0x03h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
Sets current trip blanking time, in increments of 20 ns  
0x00h: 1.00 µs  
0x32h: 1.00 µs  
7-0  
TBLANK  
8
R/W  
0x80h  
0x33h: 1.02 µs  
0xFEh: 5.10 µs  
0xFFh: 5.12 µs  
Also sets minimum on-time of PWM  
0: Disable adaptive blanking time  
1: Enable adaptive blanking time  
8
ABT  
1
3
R/W  
-
0
-
11-9  
Reserved  
Reserved  
DECAY Register  
Address = 0x04h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
7-0  
TDECAY  
8
R/W  
0x10h  
Sets mixed decay transition time, in increments of 500 ns  
000: Force slow decay at all times  
001: Slow decay for increasing current, mixed decay for  
decreasing current (indexer mode only)  
010: Force fast decay at all times  
011: Use mixed decay at all times  
100: Slow decay for increasing current, auto mixed decay for  
decreasing current (indexer mode only)  
10-8  
11  
DECMOD  
Reserved  
3
1
R/W  
1
-
101: Use auto mixed decay at all times 110 – 111: Reserved  
-
Reserved  
STALL Register  
Address = 0x05h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
Sets stall detect threshold  
The correct setting needs to be determined experimentally  
7-0  
SDTHR  
8
R/W  
0x40h  
00: STALLn asserted on first step with back EMF below SDTHR  
01: STALLn asserted after 2 steps  
10: STALLn asserted after 4 steps  
10-8  
11  
SDCNT  
VDIV  
2
2
R/W  
R/W  
0
0
11: STALLn asserted after 8 steps  
00: Back EMF is divided by 32  
01: Back EMF is divided by 16  
10: Back EMF is divided by 8  
11: Back EMF is divided by 4  
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DRIVE Register  
Address = 0x06h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
OCP threshold  
00: 250 mV  
01: 500 mV  
10: 750 mV  
11: 1000 mV  
1-0  
OCPTH  
2
R/W  
0
OCP deglitch time  
00: 1 µs  
3-2  
5-4  
OCPDEG  
TDRIVEN  
TDRIVEP  
IDRIVEN  
IDRIVEP  
2
2
2
2
2
R/W  
R/W  
R/W  
R/W  
R/W  
10  
1
01: 2 µs  
10: 4 µs  
11: 8 µs  
Low-side gate drive time  
00: 250 ns  
01: 500 ns  
10: 1 µs  
11: 2 µs  
High-side gate drive time  
00: 250 ns  
01: 500 ns  
10: 1 µs  
11: 2 µs  
7-6  
1
Low-side gate drive peak current  
00: 100 mA peak (sink)  
01: 200 mA peak (sink)  
10: 300 mA peak (sink)  
11: 40 0mA peak (sink)  
9-8  
0
High-side gate drive peak current  
00: 50 mA peak (source)  
01: 100 mA peak (source)  
10: 150 mA peak (source)  
11: 200 mA peak (source)  
11-10  
0
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STATUS Register  
Address = 0x07h  
BIT  
NAME  
SIZE  
R/W  
DEFAULT  
DESCRIPTION  
0: Normal operation  
0
OTS  
1
R
0
1: Device has entered overtemperature shutdown  
OTS bit will clear once temperature has fallen to safe levels  
0: Normal operation  
1
2
3
4
AOCP  
BOCP  
UVLO  
APDF  
1
1
1
1
R/W  
R/W  
R
0
0
0
0
1: Channel A overcurrent shutdown  
Write a ‘0’ to this bit to clear the fault and resume operation  
0: Normal operation  
1: Channel B overcurrent shutdown  
Write a ‘0’ to this bit to clear the fault and resume operation  
0: Normal operation  
1: Undervoltage lockout  
UVLO bit will clear after VM has increased over VUVLO  
0: Normal operation  
1: Channel A predriver fault  
R/W  
Write a ‘0’ to this bit to clear the fault and resume operation  
0: Normal operation  
5
6
BPDF  
STD  
1
1
R/W  
R
0
0
1: Channel B predriver fault  
Write a ‘0’ to this bit to clear the fault and resume operation  
0: Normal operation  
1: Stall detected  
0: Normal operation  
7
STDLAT  
1
4
R/W  
-
0
-
1: Latched stall detect  
Write a ‘0’ to this bit to clear the fault and resume operation  
11-8  
Reserved  
Reserved  
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PACKAGE OPTION ADDENDUM  
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28-Jun-2013  
PACKAGING INFORMATION  
Orderable Device  
DRV8711DCP  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
HTSSOP  
HTSSOP  
DCP  
38  
38  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
DRV8711  
DRV8711  
DRV8711DCPR  
ACTIVE  
DCP  
2000  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
-40 to 85  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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配单直通车
DRV8711DCPR产品参数
型号:DRV8711DCPR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
包装说明:HTSSOP,
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:1.29
Samacsys Description:Stepper Motor Gate Driver with On-Chip 1/256 Micro-Stepping Indexer and Stall Detect
模拟集成电路 - 其他类型:STEPPER MOTOR CONTROLLER
JESD-30 代码:R-PDSO-G38
JESD-609代码:e4
长度:9.7 mm
湿度敏感等级:2
功能数量:1
端子数量:38
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:HTSSOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
座面最大高度:1.2 mm
最大供电电流 (Isup):20 mA
最大供电电压 (Vsup):52 V
最小供电电压 (Vsup):8 V
标称供电电压 (Vsup):24 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:DUAL
宽度:4.4 mm
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