DS90C383AMTD全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号DS90C383AMTD的概述

DS90C383AMTD 芯片概述 DS90C383AMTD 是一款由德州仪器（Texas Instruments）推出的高性能数字视频接口转换器。该芯片能够实现经过压缩的数字信号在高速串行和并行链路之间的转换，支持多种高带宽应用，尤其是在汽车和工业视觉系统中，其灵活性和可靠性获得了广泛的应用。 DS90C383AMTD 采用先进的 CMOS 技术，具有低功耗、高集成度的特点。它可以将数字视频信号转换为差分信号，从而确保在长距离传输时信号的完整性和稳定性。该芯片广泛应用于汽车后视摄像头、工业机器视觉系统以及多媒体设备中。此外，DS90C383AMTD 还具有较强的抗干扰能力，适应各种复杂环境下的工作要求。详细参数 - 电源电压: 3.3V ± 10% - 工作温度范围: -40°C 到 +85°C - 总线类型: LVDS (低电压差分信号) - 最大传输速率: 1.5 Gbps -...

产品型号DS90C383AMTD的Datasheet PDF文件预览

July 1998

DS90C383A/DS90CF383A

+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel

Display (FPD) Link-65 MHz

+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD)

Link-65 MHz

1.0 General Description

2.0 Features

n 20 to 65 MHz shift clock support

The DS90C383A/DS90CF383A transmitter converts 28 bits

of CMOS/TTL data into four LVDS (Low Voltage Differential

Signaling) data streams. A phase-locked transmit clock is

transmitted in parallel with the data streams over a fifth

LVDS link. Every cycle of the transmit clock 28 bits of input

data are sampled and transmitted. At a transmit clock fre-

quency of 65 MHz, 24 bits of RGB data and 3 bits of LCD

timing and control data (FPLINE, FPFRAME, DRDY) are

transmitted at a rate of 455 Mbps per LVDS data channel.

Using a 65 MHz clock, the data throughput is 227 Mbytes/

sec. The DS90C383A transmitter can be programmed for

Rising edge strobe or Falling edge strobe through a dedi-

cated pin. The DS90CF383A is fixed as a Falling edge

strobe transmitter. A Rising edge or Falling edge strobe

transmitter will interoperate with a Falling edge strobe Re-

ceiver (DS90CF384) without any translation logic.

> ±

n Rejects

225ps output Jitter 65MHz (TJCC)

3ns Jitter from VGA chip with less than

n Best–in–Class Set & Hold Times on TxINPUTs

n Tx power consumption 130 mW (typ) 65MHz

Grayscale

50% Less Power Dissipation than BiCMOS

Alternatives

n Tx Power-down mode 200µW (max)

n ESD rating 7 kV (HBM), 500V (EIAJ)

n Supports VGA, SVGA, XGA and Dual Pixel SXGA.

n Narrow bus reduces cable size and cost

n Up to 1.8 Gbps throughput

n Up to 227 Megabytes/sec bandwidth

n 345 mV (typ) swing LVDS devices for low EMI

n PLL requires no external components

n Compatible with TIA/EIA-644 LVDS standard

n Low profile 56-lead TSSOP package

n Improved replacement for:

This chipset is an ideal means to solve EMI and cable size

problems associated with wide, high speed TTL interfaces.

SN75LVDS83 — DS90C383A

SN75LVDS81 — DS90CF383A

3.0 Block Diagrams

DS90C383A/DS90CF383A

DS100100-1

Order Number DS90C383AMTD or DS90CF383AMTD

See NS Package Number MTD56

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100100

www.national.com

4.0 Absolute Maximum Ratings (Note

Package Derating:

DS90C383A/DS90CF383A

12.5 mW/˚C above +25˚C

ESD Rating

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

(HBM, 1.5 kΩ, 100 pF)

(EIAJ, 0Ω, 200 pF)

7 kV

500V

Supply Voltage (V_CC

)

−0.3V to +4V

−0.3V to (V_CC+ 0.3V)

5.0 Recommended Operating

Conditions

CMOS/TTL Input Voltage

LVDS Driver Output Voltage

Min Nom Max

Units

LVDS Output Short Circuit

Duration

Continuous

+150˚C

Supply Voltage (V_CC

Operating Free Air

Temperature (T_A)

)

3.0

3.3

3.6

Junction Temperature

Storage Temperature

−65˚C to +150˚C

−10 +25 +70

2.4

˚C

Lead Temperature

(Soldering, 4 sec)

Receiver Input Range

Supply Noise Voltage (V_CC

TxCLKIN frequency

+260˚C

)

100 mV_PP

68 MHz

Maximum Package Power Dissipation Capacity 25˚C

MTD56 (TSSOP) Package:

DS90C383A/DS90CF383A

1.63 W

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CMOS/TTL DC SPECIFICATIONS

V_IH

V_IL

V_CL

I_IN

High Level Input Voltage

Low Level Input Voltage

Input Clamp Voltage

Input Current

2.0

V_CC

0.8

GND

I_CL= −18 mA

−0.79

+1.8

−1.5

+10

= 0.4V, 2.5V or V_CC

= GND

µA

−10

250

LVDS DC SPECIFICATIONS

V_OD

Differential Output Voltage

R_L= 100Ω

345

1.25

−3.5

450

∆V_OD

Change in V_ODbetween

complimentary output states

V_OS

Offset Voltage (Note 4)

1.125

1.375

∆V_OS

Change in V_OSbetween

complimentary output states

I_OS

I_OZ

Output Short Circuit Current

Output TRI-STATE^®Current

V_OUT= 0V, R_L= 100Ω

−5

µA

Power Down = 0V,

V_OUT= 0V or V_CC

TRANSMITTER SUPPLY CURRENT

ICCTW

ICCTG

ICCTZ

Transmitter Supply Current

Worst Case

R_L= 100Ω,

C_L= 5 pF,

Worst Case Pattern

(Figures 1, 4)

f = 32.5 MHz

f = 37.5 MHz

f = 65 MHz

µA

Transmitter Supply Current

16 Grayscale

R_L= 100Ω,

C_L= 5 pF,

16 Grayscale Pattern

(Figures 2, 4)

f = 32.5 MHz

f = 37.5 MHz

f = 65 MHz

Transmitter Supply Current

Power Down

Power Down = Low

Driver Outputs in TRI-STATE under

Power Down Mode

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device

should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V

= 3.3V and T = +25C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V and ∆V ).

Note 4:

previously referred as V .

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Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

TCIT

Parameter

TxCLK IN Transition Time (Figure 5 )

Min

Typ

Max Units

TCIP

TxCLK IN Period (Figure 6 )

TxCLK IN High Time (Figure 6 )

TxCLK IN Low Time (Figure 6)

14.7

0.35T

55.6

TCIH

TCIL

0.5T 0.65T

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

LLHT

Parameter

LVDS Low-to-High Transition Time (Figure 4 )

LVDS High-to-Low Transition Time (Figure 4 )

Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)

Transmitter Output Pulse Position for Bit 1

Transmitter Output Pulse Position for Bit 2

Transmitter Output Pulse Position for Bit 3

Transmitter Output Pulse Position for Bit 4

Transmitter Output Pulse Position for Bit 5

Transmitter Output Pulse Position for Bit 6

Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)

Transmitter Output Pulse Position for Bit 1

Transmitter Output Pulse Position for Bit 2

Transmitter Output Pulse Position for Bit 3

Transmitter Output Pulse Position for Bit 4

Transmitter Output Pulse Position for Bit 5

Transmitter Output Pulse Position for Bit 6

Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)

Transmitter Output Pulse Position for Bit 1

Transmitter Output Pulse Position for Bit 2

Transmitter Output Pulse Position for Bit 3

Transmitter Output Pulse Position for Bit 4

Transmitter Output Pulse Position for Bit 5

Transmitter Output Pulse Position for Bit 6

TxIN Setup to TxCLK IN (Figure 6 )

Min

Typ

0.75

Max Units

1.5

LHLT

TPPos0

TPPos1

TPPos2

TPPos3

TPPos4

TPPos5

TPPos6

TPPos0

TPPos1

TPPos2

TPPos3

TPPos4

TPPos5

TPPos6

TPPos0

TPPos1

TPPos2

TPPos3

TPPos4

TPPos5

TPPos6

TSTC

65 MHz

−0.30

1.90

4.10

6.30

8.50

0.20

2.40

4.60

6.80

9.00

2.20

4.40

6.60

8.80

10.70 11.00 11.20

12.90 13.20 13.40

40 MHz

−0.35

3.22

0.35

3.92

7.49

3.57

7.14

6.79

10.36 10.71 11.06

13.93 14.28 14.63

17.51 17.86 18.21

21.08 21.43 21.78

32.5

−0.40

4.00

0.40

4.80

9.20

MHz

4.40

8.80

8.40

12.80 13.20 13.60

17.20 17.60 18.00

21.60 22.00 22.40

26.00 26.40 26.80

2.5

THTC

TxIN Hold to TxCLK IN (Figure 6 )

TCCD

TxCLK IN to TxCLK OUT Delay (Figure 7 ) T_A=25˚C,V_CC=3.3V

TxCLK IN to TxCLK OUT Delay (Figure 7 )

Transmitter Jitter Cycle-to-Cycle (Figures 12, 13 ) (Note 6)

5.5

7.0

TJCC

65 MHz

40 MHz

175

240

260

225

380

400

32.5

MHz

TPLLS

TPDD

Transmitter Phase Lock Loop Set (Figure 8 )

Transmitter Power Down Delay (Figure 10 )

100

Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This param-

eter is functionality tested only on Automatic Test Equipment (ATE).

Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycle-

to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips

currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.

www.national.com

6.0 AC Timing Diagrams

DS100100-4

FIGURE 1. “Worst Case” Test Pattern

DS100100-5

FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)

Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).

Note 10: Recommended pin to signal mapping. Customer may choose to define differently.

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6.0 AC Timing Diagrams (Continued)

DS100100-30

FIGURE 3. DS90C383A/DS90CF383A (Transmitter) LVDS Output Load

DS100100-6

FIGURE 4. DS90C383A/DS90CF383A (Transmitter) LVDS Transition Times

DS100100-8

FIGURE 5. DS90C383A/DS90CF383A (Transmitter) Input Clock Transition Time

DS100100-10

FIGURE 6. DS90C383A/DS90CF383A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)

DS100100-12

FIGURE 7. DS90C383A/DS90CF383A (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)

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6.0 AC Timing Diagrams (Continued)

DS100100-14

FIGURE 8. DS90C383A/DS90CF383A (Transmitter) Phase Lock Loop Set Time

DS100100-17

FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs

DS100100-18

FIGURE 10. Transmitter Power Down Delay

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6.0 AC Timing Diagrams (Continued)

DS100100-26

FIGURE 11. Transmitter LVDS Output Pulse Position Measurement

DS100100-27

FIGURE 12. TJCC Test Setup

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6.0 AC Timing Diagrams (Continued)

DS100100-28

FIGURE 13. Timing Diagram of the Input cycle-to-cycle clock jitter

7.0 DS90C383A Pin Description— FPD Link Transmitter

Pin Name

TxIN

I/O No.

Description

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

Positive LVDS differentiaI data output.

TxOUT−

Negative LVDS differential data output.

FPSHIFT IN

R_FB

TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.

Programmable strobe select (See Table 1).

Positive LVDS differential clock output.

TxCLK OUT+

TxCLK OUT−

PWR DOWN

Negative LVDS differential clock output.

TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

power down.

V_CC

Power supply pins for TTL inputs.

Ground pins for TTL inputs.

Power supply pin for PLL.

GND

PLL V_CC

PLL GND

LVDS V_CC

LVDS GND

Ground pins for PLL.

Power supply pin for LVDS outputs.

Ground pins for LVDS outputs.

8.0 DS90CF383A Pin Description— FPD Link Transmitter

Pin Name

TxIN

I/O No.

Description

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

Positive LVDS differential data output.

TxOUT−

Negative LVDS differential data output.

FPSHIFT IN

TxCLK OUT+

TxCLK OUT−

PWR DOWN

TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.

Positive LVDS differential clock output.

Negative LVDS differential clock output.

TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

power down.

V_CC

Power supply pins for TTL inputs.

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8.0 DS90CF383A Pin Description— FPD Link Transmitter (Continued)

Pin Name

GND

I/O No.

Description

Ground pins for TTL inputs.

Power supply pin for PLL.

Ground pins for PLL.

PLL V_CC

PLL GND

LVDS V_CC

LVDS GND

Power supply pin for LVDS outputs.

Ground pins for LVDS outputs.

9.0 Applications Information

The DS90C383A/DS90CF383A are backward compatible

with the DS90C383/DS90CF383 and are a pin-for-pin re-

placement. The device (DS90C383A/DS90CF383A) utilizes

a different PLL architecture employing an internal 7X clock

for enhanced pulse position control.

1. Change 5V power supply to 3.3V. Provide this supply to

the V_CC, LVDS V_CCand PLL V_CCof the transmitter.

2. The DS90C383A transmitter input and control inputs ac-

cept 3.3V TTL/CMOS levels. They are not 5V tolerant.

3. To implement a falling edge device for the DS90C383A,

the R_FB pin (pin 17) may be tied to ground OR left un-

connected (an internal pull-down resistor biases this pin

low). Biasing this pin to Vcc implements a rising edge

device.

This device (DS90C383A/DS90CF383A) also features re-

duced variation of the TCCD parameter which is important

for dual pixel applications. (See AN-1084) TCCD variation

has been measured to be less than 250ps at 65MHz under

normal operating conditions.

This device may also be used as a replacement for the

DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)

FPD-Link Transmitters with certain considerations/

modifications:

10.0 Transmitter Clock Jitter Cycle-to-Cycle

Figures 12 and 13 illustrate the timing of the input clock rela-

tive to the input data. The input clock (TxCLKin) is intention-

ally shifted to the left −3ns and +3ns to the right when data

(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-

peated at a period of 2µs, which is the period of the input

data (1µs high, 1µs low). At different operating frequencies

the N Cycle is changed to maintain the desired 3ns cycle-to-

cycle jitter at 2µs period.

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11.0 Pin Diagram

DS90C383A

DS90CF383A

DS100100-23

DS100100-24

Application

DS100100-3

TABLE 1. Programmable Transmitter (DS90C383A)

Condition

R_FB = V_CC

R_FB = GND or NC

Strobe Status

Rising edge strobe

Falling edge strobe

R_FB

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12.0 Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90C383AMTD, DS90CF383AMTD

NS Package Number MTD56

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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DS90C383AMTD产品参数

型号:	DS90C383AMTD
是否Rohs认证：	不符合
生命周期：	Obsolete
包装说明：	TSSOP, TSSOP56,.3,20
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.06
Is Samacsys：	N
差分输出：	YES
驱动器位数：	5
输入特性：	STANDARD
接口集成电路类型：	LINE DRIVER
接口标准：	EIA-644; TIA-644
JESD-30 代码：	R-PDSO-G56
JESD-609代码：	e0
长度：	14 mm
功能数量：	5
端子数量：	56
最高工作温度：	70 °C
最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP56,.3,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
认证状态：	Not Qualified
最大接收延迟：
座面最大高度：	1.1 mm
子类别：	Line Driver or Receivers
最大压摆率：	52 mA
最大供电电压：	3.6 V
最小供电电压：	3 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6.1 mm
Base Number Matches：	1

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